AT&T PC 6300 - Page 45

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SYSTEM OVERVIEW
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Interrupt Controller
Hardware Interrupts are asynchronous events requiring CPU
attention and are generally started by peripheral devices requiring
service. The CPU is normally allowed to execute its main program
until an interrupt request occurs. On receipt of an interrupt
request, the CPU completes the instruction being executed, saves
its current state (instruction pointer, code segment, and flags), and
fetches a new routine to service the interrupting device. Once the
interrupting device has been serviced, the CPU resumes its main
program at the point where it was interrupted.
The system has nine interrupts in all: eight maskable interrupts
and one nonmaskable interrupt. The nonmaskable interrupt has
priority over the maskable interrupts. The maskable interrupts
have a specific priority level assigned to each of them. It is the job
of the interrupt controller to handle the priority of the maskable
interrupts. It functions as an overall manager in the interrupt-
driven system environment to choose which interrupt gets service
first according to their priority levels. The interrupt controller
used is the Intel 8259 (or equivalent).
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