BONFIGLIOLI Agile - 201] Bit AND;NAND Operation

VPLC / PLC 12708/10
08/10 VPLC / PLC 127
Example: I1 = 0xF00F
Æ O1 = 0x0FF0, O2 = 0xF00F
Master Set sets all bits of the output value (Output = 0xFFFF).
Master Reset deletes all bits of the output value (Output = 0x0000).
Note:
Since output I2 output the bitwise inverted value of output O1, O2 = I1.
5.11.2 [201] Bit AND/NAND operation
Type Function Type Function
I1 % input value 1 O1 %
O1=AND (I1 I2) if P2=1,
O1=AND (I1 P1) if P2=2,
O1=AND (I1 I2 P1) if P2=3
I2 % input value 2 O2 % inverted output = (NAND)
I3 b Master Set P1 % Mask
I4 b Master Reset P2 i Operation mode (1, 2 or 3)
Description:
The input value at I1 is AND combined. Via P2, you can select:
−
P2 = 1: I1 and I2 are AND combined.
− P2 = 2: I1 and P1 are AND combined.
− P2 = 3: I1, I2 and P1 are AND combined.
Master Set sets all bits of the output value (Output = 0xFFFF).
Master Reset deletes all bits of the output value (Output = 0x0000).
Examples:
P2 I1 I2 P1 O1 O2
1) AND (I1 I2) 0xF00F 0x0F0F - 0x000F 0xFFF0
2) AND (I1 P1) 0xF00F - 0x00FF 0x000F 0xFFF0
3) AND (I1 I2 P1) 0xF00F 0x0F0F 0x00FF 0x000F 0xFFF0