BONFIGLIOLI Agile

VPLC / PLC 08/10142
142 VPLC / PLC 08/10
6.5 Example 3: Parameterization of logic diagram
Inverter Release
S2IND
S1OUT
S3IND
S4IND
&
=1
1
S5IND
70 -
Inverter Release
71 -
S2IND
FT-input buffer 1362
2 - OR
FT-instruction 1343
2002
2003
FT-output 1 1350
FT-output 1 1351
OR
Index 1
Index 1
Function Table
Function Table: Input Buffer
Index 2
72 -
S3IND
2101
2001
1 - AND
AND
VTable
FT-input 3 1346
VPlus
FT-input 2 1345
FT-input 1 1344
FT-input 4 1347
Index 2 Index 3
Index 1
Index 2
Index 3
Index 4 Index 5
73 -
S4IND
74 -
S5IND
Index 3
2005
2004
2102
3 - XOR 1
XOR 1
2401
Op. Mode Digital Output 1 530 = 80 - FT-Output Buffer 1