BONFIGLIOLI Agile - 30] D-Flip-Flop, Superior

VPLC / PLC 08/1056
56 VPLC / PLC 08/10
4.4.5 [30] D-Flip-Flop, Superior
Type Function Type Function
I1
b C, Clock
O1
b output O1
I2
b D, Data input
O2
b
negated output O2 =
1O
I3
b Superior Set input
P1
I4
b Superior Reset input
P2
Description:
If a positive edge is received at input 1 (clock pulse input C, Clock) the signal is transferred
from signal input 2 (data input D) to the output.
TRUE at the Superior Set input sets the output to TRUE. TRUE at the Superior Reset input sets
the output to FALSE.
Via the output buffer, the output signal is globally available.
Inputs Superior Set and Superior Reset are connected in series with the function. Levels on C
input I1 and D input I2 are processed internally. As soon as the Superior Set or Superior Reset
is reset, the output is switched to the internally saved value.
D-Flip-Flop, Superior
C D SS SR
O1
Q
State
x x x 1 0 Off (Superior)
x x 1 0 1 On (Superior)
x x 0 0 Q
n-1
Hold
0Æ1
0 0 0 0 Sample
0Æ1 1 0 0 1 Sample