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BONFIGLIOLI Agile Applications Manual

BONFIGLIOLI Agile
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VPLC / PLC 5308/10
08/10 VPLC / PLC 53
4.4.2 [110] RS-Flip-Flop, Master
Type Function
Type Function
I1
b Set input
O1
b output O1
I2
b Reset input
O2
b
negated output O2 =
1O
I3
b Master Set input
P1
I4
b Master Reset input
P2
Description:
The inputs of the instruction are the assigned signal sources.
TRUE at the Set input sets the output to TRUE. TRUE at the Reset input sets the output to
FALSE. If FALSE is present on both inputs, the current status of the output signal is maintained.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Priority:
Master Reset (highest priority)
Master Set
Reset
Set (lowest priority)
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
RS-Flip-Flop, Master
S
R
MS
MR
O1
Q
State
x x X 1 0 Off (Master)
X X 1 0 1 On (Master)
0 0 0 0 Q
n-1
Hold
0 1 0 0 0 Reset
1 0 0 0 1 Set
1 1 0 0 0 Off
Set: TRUE at the S input sets the output to TRUE.
Save: If all inputs are FALSE, the output remains unchanged.
Reset: If R input is TRUE, the output is set to logic FALSE.
Off: If both inputs are set to TRUE, the output is FALSE.
Master-Set: MS, set output to TRUE.
Master-Reset: MR, set output to FALSE (CLR).

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BONFIGLIOLI Agile Specifications

General IconGeneral
BrandBONFIGLIOLI
ModelAgile
CategoryDC Drives
LanguageEnglish

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