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BONFIGLIOLI Agile Applications Manual

BONFIGLIOLI Agile
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VPLC / PLC 08/1068
68 VPLC / PLC 08/10
4.6.4 [170,171,172] Monoflop (non-retriggerable), Master
Type Function
Type Function
I1
b M, Monoflop edge 1
O1
b output O1
I2
b , Monoflop edge 2
O2
b
negated output O2 =
1O
I3
b Master Set input
P1
t On-time (High)
I4
b Master Reset input
P2
t ignore edge time
170 [ms], 171 [s] or 172 [min]
Description:
Output signal becomes TRUE with positive clock edge at input 1 or with negative clock edge at
input 2. The time set in P1 is the On-Time (High) and the time set in P2 is the ignore edge time
(Low). The set on-time starts again with each edge.
TRUE at the Master Set input sets the output to TRUE. TRUE at the Master Reset input sets the
output to FALSE.
Via the output buffer, the output signal is globally available.
Master Set and Master Reset are connected parallel with the function and change the state of
the function as soon as the signal is present.
Monoflop (non-retriggerable), Master
I1
M
I2
I3
MS
I4
MR
O1
Q
State
x x x 1 0 Off (Master)
x x 1 0 1 On (Master)
0Æ1 x 0 0 Pulse
x 1Æ0 0 0 Pulse
P1
(on-time)
P2
(ignore edge time)

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BONFIGLIOLI Agile Specifications

General IconGeneral
BrandBONFIGLIOLI
ModelAgile
CategoryDC Drives
LanguageEnglish

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