Bouffalo Lab BL702 - Page 174

BL702/704/706 Reference Manual
8.4.15 irrx_config
Address：0x4000a680
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RXDEGCNT RSVD RXDG
EN
RXMODE RXIN
INV
RXEN
Bits
Name Type Reset Description
31:12 RSVD
11:8 RXDEGCNT R/W 4’d0 De-glitch function cycle count
7:5 RSVD
4 RXDGEN R/W 1’b0 Enable signal of IRRX input de-glitch function
3:2 RXMODE R/W 2’d0 IRRX mode
0: NEC
1: RC5
2: SW pulse-width detection mode (SWM)
3: Reserved
1 RXININV R/W 1’b1 Input inverse signal
0 RXEN R/W 1’b0 Enable signal of IRRX function
Asserting this bit will trigger the transaction, and should be
de-asserted after finish
8.4.16 irrx_int_sts
Address：0x4000a684
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD RXE
EN
RSVD RXE
CLR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RXE
MASK
RSVD RXE
INT
Bits
Name Type Reset Description
31:25 RSVD
24 RXEEN R/W 1’b1 Interrupt enable of irrx_end_int
BL702/704/706 Reference Manual 174/ 375
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