EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-36
A potential problem exists if the external device is writing to an address in external memory, and
at the same time the Intel486 processor is reading data from the same address in the second-level
cache. The system must force an invalidation cycle to invalidate the data that the Intel486 pro-
cessor has requested during the line fill.
Figure 4-27. System with Second-Level Cache
Intel486™
Processor
Second-Level
Cache
System Bus
External
Memory
External Bus
Master
Address, Data and
Control Bus
Address, Data and
Control Bus
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