EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-42
The latency between a STPCLK# request and the Stop Grant bus cycle is dependent on the cur-
rent instruction, the amount of data in the processor write buffers, and the system memory per-
formance.
Figure 4-32. Stop Grant Bus Cycle
Table 4-9. Special Bus Cycle Encoding
Cycle Name M/IO# D/C# W/R# BE3#–BE0# A4-A2
Write-Back
†
0 0 1 0111 000
First Flush Ack Cycle
†
0 0 1 0111 001
Flush
†
0 0 1 1101 000
Second Flush Ack Cycle
†
0 0 1 1101 001
Shutdown 0 0 1 1110 000
HALT 0 0 1 1011 000
Stop Grant Ack Cycle 0 0 1 1011 100
†
These cycles are specific to the Write-Back Enhanced IntelDX4™ processor. The FLUSH# cycle is
applicable to all Intel486™ processors. See appropriate sections for details.
STPCLK#
CLK
A4401-01
Stop Grant Cycle
BRDY# or RDY#
ADDR Data
T
hd
T
su
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