Intel Embedded Intel486

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CONTENTS
FIGURES
Figure Page
2-1 A Typical Intel486™ Processor System .......................................................................2-8
2-2 Single-Processor System .............................................................................................2-9
2-3 Loosely Coupled Multi-processor System ..................................................................2-10
2-4 External Cache...........................................................................................................2-11
2-5 Embedded Personal Computer and Embedded Controller Example .........................2-12
3-1 IntelDX2™ and IntelDX4™ Processors Block Diagram ...............................................3-2
3-2 Intel486™ SX Processor Block Diagram......................................................................3-3
3-3 Ultra-Low Power Intel486™ SX and Ultra-Low Power Intel486 GX Processors
Block Diagram..............................................................................................................3-4
3-4 Internal Pipelining.........................................................................................................3-7
3-5 Cache Organization....................................................................................................3-11
3-6 Segmentation and Paging Address Formats..............................................................3-16
3-7 Translation Lookaside Buffer......................................................................................3-17
4-1 Physical Memory and I/O Spaces ................................................................................4-2
4-2 Physical Memory and I/O Space Organization.............................................................4-3
4-3 Intel486™ Processor with 32-Bit Memory ....................................................................4-5
4-4 Addressing 16- and 8-Bit Memories .............................................................................4-6
4-5 Logic to Generate A1, BHE# and BLE# for 16-Bit Buses.............................................4-8
4-6 Data Bus Interface to 16- and 8-Bit Memories .............................................................4-9
4-7 Single Master Intel486™ Processor System..............................................................4-12
4-8 Single Intel486™ Processor with DMA.......................................................................4-13
4-9 Single Intel486™ Processor with Multiple Secondary Masters..................................4-14
4-10 Basic 2-2 Bus Cycle ...................................................................................................4-16
4-11 Basic 3-3 Bus Cycle ...................................................................................................4-17
4-12 Non-Cacheable, Non-Burst, Multiple-Cycle Transfers................................................4-20
4-13 Non-Cacheable Burst Cycle.......................................................................................4-21
4-14 Non-Burst, Cacheable Cycles ....................................................................................4-23
4-15 Burst Cacheable Cycle...............................................................................................4-24
4-16 Effect of Changing KEN# ...........................................................................................4-25
4-17 Slow Burst Cycle ........................................................................................................4-26
4-18 Burst Cycle Showing Order of Addresses ..................................................................4-27
4-19 Interrupted Burst Cycle...............................................................................................4-28
4-20 Interrupted Burst Cycle with Non-Obvious Order of Addresses .................................4-29
4-21 8-Bit Bus Size Cycle...................................................................................................4-30
4-22 Burst Write as a Result of BS8# or BS16#.................................................................4-31
4-23 Locked Bus Cycle.......................................................................................................4-32
4-24 Pseudo Lock Timing...................................................................................................4-33
4-25 Fast Internal Cache Invalidation Cycle.......................................................................4-34
4-26 Typical Internal Cache Invalidation Cycle...................................................................4-35
4-27 System with Second-Level Cache..............................................................................4-36
4-28 Cache Invalidation Cycle Concurrent with Line Fill ....................................................4-37
4-29 HOLD/HLDA Cycles ...................................................................................................4-38
4-30 HOLD Request Acknowledged during BOFF# ...........................................................4-39
4-31 Interrupt Acknowledge Cycles....................................................................................4-40