EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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CHAPTER 10
PHYSICAL DESIGN AND SYSTEM DEBUGGING
10.1 GENERAL SYSTEM GUIDELINES ............................................................................. 10-1
10.2 POWER DISSIPATION AND DISTRIBUTION............................................................. 10-1
10.2.1 Power and Ground Planes.......................................................................................10-2
10.3 HIGH-FREQUENCY DESIGN CONSIDERATIONS.................................................... 10-9
10.3.1 Transmission Line Effects........................................................................................10-9
10.3.1.1 Transmission Line Types ..................................................................................10-10
10.3.1.2 Micro-Strip Lines ...............................................................................................10-10
10.3.1.3 Strip Lines .........................................................................................................10-11
10.3.2 Impedance Mismatch.............................................................................................10-12
10.3.2.1 Impedance Matching.........................................................................................10-18
10.3.2.2 Daisy Chaining ..................................................................................................10-24
10.3.2.3 90-Degree Angles .............................................................................................10-24
10.3.2.4 Vias (Feed-Through Connections)....................................................................10-25
10.3.3 Interference............................................................................................................10-25
10.3.3.1 Electromagnetic Interference (EMI)...................................................................10-25
10.3.3.2 Minimizing Electromagnetic Interference ..........................................................10-26
10.3.3.3 Electrostatic Interference ..................................................................................10-28
10.3.4 Propagation Delay .................................................................................................10-29
10.4 LATCH-UP................................................................................................................. 10-30
10.5 CLOCK CONSIDERATIONS ..................................................................................... 10-30
10.5.1 Requirements.........................................................................................................10-31
10.5.2 Routing...................................................................................................................10-31
10.6 THERMAL CHARACTERISTICS............................................................................... 10-33
10.7 DERATING CURVE AND ITS EFFECTS .................................................................. 10-36
10.8 BUILDING AND DEBUGGING THE Intel486™ PROCESSOR-BASED SYSTEM.... 10-37
10.8.1 Debugging Features of the Intel486™ Processor..................................................10-39
10.8.2 Breakpoint Instruction ............................................................................................10-39
10.8.3 Single-Step Trap ....................................................................................................10-39
10.8.4 Debug Registers ....................................................................................................10-39
10.8.5 Debug Control Register (DR7)...............................................................................10-42
10.8.6 Debugging Overview..............................................................................................10-43
INDEX
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