ix
CONTENTS
8.4.5.5 Cycle Shortening.................................................................................................8-31
8.4.5.6 Status and Control Interface ...............................................................................8-32
8.4.6 DMA Controller ........................................................................................................8-33
8.4.6.1 DMA Status and Control Interface ......................................................................8-34
CHAPTER 9
PERFORMANCE CONSIDERATIONS
9.1 INTRODUCTION ........................................................................................................... 9-1
9.1.1 Memory Performance Factors....................................................................................9-1
9.2 INSTRUCTION EXECUTION PERFORMANCE ........................................................... 9-2
9.2.1 Intel486™ Processor Execution Times......................................................................9-2
9.2.2 Application Programs Used in Analysis .....................................................................9-4
9.3 INTERNAL CACHE PERFORMANCE ISSUES ............................................................ 9-4
9.3.1 On-Chip Cache Organization Issues..........................................................................9-4
9.3.2 Performance Effects of the On-Chip Cache...............................................................9-5
9.3.3 Bus Cycle Mix with and without On-Chip Cache........................................................9-6
9.4 ON-CHIP WRITE BUFFERS ......................................................................................... 9-7
9.5 EXTERNAL MEMORY CONSIDERATIONS ................................................................. 9-8
9.5.1 Introduction ................................................................................................................9-8
9.5.2 Wait States in Burst and Non-Burst Modes................................................................9-9
9.5.3 Impact of Wait States on Performance ....................................................................9-10
9.5.4 Bus Utilization and Wait States................................................................................9-10
9.6 SECOND-LEVEL CACHE PERFORMANCE CONSIDERATIONS............................. 9-11
9.6.1 Advantages of a Second-Level Cache.....................................................................9-11
9.6.2 An Example of a Second-Level Cache ....................................................................9-12
9.6.3 System Performance with a Second-Level Cache...................................................9-12
9.6.4 Impact of Second-Level Cache on Bus Utilization ...................................................9-13
9.7 DRAM DESIGN TECHNIQUES................................................................................... 9-14
9.8 EXTENDED DATA OUTPUT RAM (EDO RAM).......................................................... 9-14
9.8.1 Interleaving ..............................................................................................................9-14
9.8.2 Impact of Performance for Posted Write Cycles ......................................................9-15
9.9 FLOATING-POINT PERFORMANCE.......................................................................... 9-16
9.9.1 Floating-Point Execution Sequences .......................................................................9-16
9.9.2 Performance of the Floating-Point Unit....................................................................9-17
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