Intel Embedded Intel486 User Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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7.6.2 82557 High Speed LAN Controller Interface............................................................7-50
7.6.2.1 82557 Overview ..................................................................................................7-50
7.6.2.2 Features and Enhancements ..............................................................................7-51
7.6.2.3 PCI Bus Interface ................................................................................................7-52
7.6.2.4 82557 Bus Operations ........................................................................................7-52
7.6.2.5 Initializing the 82557 ...........................................................................................7-52
7.6.2.6 Controlling the 82557..........................................................................................7-53
CHAPTER 8
SYSTEM BUS DESIGN
8.1 INTRODUCTION ........................................................................................................... 8-1
8.2 SYSTEM BUS INTERFACE .......................................................................................... 8-1
8.3 EISA BUS: SYSTEM DESIGN EXAMPLE..................................................................... 8-2
8.3.1 Introduction to the EISA Architecture.........................................................................8-2
8.3.2 An Example EISA Chip Set........................................................................................8-3
8.3.3 EBC Host Bus Interface .............................................................................................8-9
8.3.3.1 Clock, Control and Status Interface ......................................................................8-9
8.3.3.2 Host Local Memory and I/O Interface .................................................................8-10
8.3.3.3 Host Bus Acquisition and Release ......................................................................8-10
8.3.3.4 Lock, Snoop, and Address Greater than 16 Mbytes ...........................................8-10
8.3.4 EISA/ISA Bus Interface to the EBC .........................................................................8-11
8.3.4.1 EBC and EISA Bus Interface Signals..................................................................8-11
8.3.4.2 EBC and ISA Bus Interface Signals....................................................................8-12
8.3.5 EBC and ISP Interface.............................................................................................8-13
8.3.6 EBC and EBB Data and Address Buffer Controls....................................................8-14
8.3.6.1 Functions of the ISP............................................................................................8-16
8.3.6.2 ISP-to-Host Interface...........................................................................................8-17
8.3.7 ISP-to-EISA Interface...............................................................................................8-17
8.4 PCI BUS: SYSTEM DESIGN EXAMPLE..................................................................... 8-19
8.4.1 Introduction to PCI Architecture ...............................................................................8-19
8.4.2 Example PCI System Design...................................................................................8-19
8.4.3 Host CPU Interface ..................................................................................................8-24
8.4.3.1 Host Bus Slave Device........................................................................................8-24
8.4.3.2 L1 Cache Support ...............................................................................................8-24
8.4.3.3 Control and Status Interface ...............................................................................8-24
8.4.3.4 PCI Bus Cycles Support......................................................................................8-26
8.4.3.5 Host to PCI Cycles ..............................................................................................8-27
8.4.3.6 Exclusive Cycles .................................................................................................8-27
8.4.3.7 Status and Control Interface ...............................................................................8-28
8.4.4 System Controller/ISA Bridge Link Interface............................................................8-29
8.4.4.1 Status and Control Interface ...............................................................................8-29
8.4.5 ISA Interface ............................................................................................................8-30
8.4.5.1 I/O Recovery Support..........................................................................................8-30
8.4.5.2 SYSCLK Generation ...........................................................................................8-30
8.4.5.3 Data Byte Swapping (ISA Master or DMA to ISA Device)...................................8-30
8.4.5.4 Wait-State Generation.........................................................................................8-31

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English