Intel Embedded Intel486

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CONTENTS
CHAPTER 7
PERIPHERAL SUBSYSTEM
7.1 PERIPHERAL/PROCESSOR BUS INTERFACE .......................................................... 7-1
7.1.1 Mapping Techniques..................................................................................................7-1
7.1.2 Dynamic Bus Sizing ...................................................................................................7-3
7.1.3 Address Decoding for I/O Devices.............................................................................7-5
7.1.3.1 Address Bus Interface...........................................................................................7-6
7.1.3.2 8-Bit I/O Interface..................................................................................................7-7
7.1.3.3 16-Bit I/O Interface ..............................................................................................7-10
7.1.3.4 32-Bit I/O Interface ..............................................................................................7-14
7.2 BASIC PERIPHERAL SUBSYSTEM ........................................................................... 7-17
7.2.1 Bus Control and Ready Logic ..................................................................................7-20
7.2.2 Bus Control Signal Description ................................................................................7-21
7.2.2.1 Processor Interface .............................................................................................7-21
7.2.2.2 Wait State Generation Signals ............................................................................7-22
7.2.3 Wait State Generator Logic......................................................................................7-22
7.2.4 Address Decoder .....................................................................................................7-23
7.2.5 Data Transceivers....................................................................................................7-26
7.2.6 Recovery and Bus Contention .................................................................................7-26
7.2.7 Write Buffers and I/O Cycles....................................................................................7-27
7.2.7.1 Write Buffers and Recovery Time .......................................................................7-27
7.2.8 Non-Cacheability of Memory-Mapped I/O Devices..................................................7-27
7.2.9 Intel486™ Processor On-Chip Cache Consistency .................................................7-28
7.3 I/O CYCLES................................................................................................................. 7-29
7.3.1 Read Cycle Timing...................................................................................................7-29
7.3.2 Write Cycle Timings .................................................................................................7-31
7.4 DIFFERENCE BETWEEN THE Intel486™ DX PROCESSOR FAMILY
AND Intel386™ PROCESSORS...................................................................................7-33
7.5 INTERFACING TO
x 86 PERIPHERALS...................................................................... 7-34
7.5.1 Universal Peripheral Interface..................................................................................7-34
7.5.2 82C59A Interface.....................................................................................................7-35
7.5.2.1 Single Interrupt Controller ...................................................................................7-35
7.5.2.2 Cascaded Interrupt Controllers ...........................................................................7-37
7.5.2.3 Handling More than 64 Interrupts........................................................................7-38
7.6 Intel486™ PROCESSOR LAN CONTROLLER INTERFACE...................................... 7-38
7.6.1 82596CA Coprocessor.............................................................................................7-38
7.6.1.1 Hardware Interface..............................................................................................7-41
7.6.1.2 Processor and Coprocessor Interaction..............................................................7-44
7.6.1.3 Memory Structure................................................................................................7-46
7.6.1.4 Media Access......................................................................................................7-46
7.6.1.5 Transmit and Receive Operation ........................................................................7-47
7.6.1.6 Bus Throttle Timers.............................................................................................7-47
7.6.1.7 Design Considerations ........................................................................................7-48
7.6.1.8 82596 Co-processor Performance......................................................................7-49