EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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CHAPTER 5
MEMORY SUBSYSTEM DESIGN
5.1 INTRODUCTION ........................................................................................................... 5-1
5.2 PROCESSOR AND CACHE FEATURE OVERVIEW.................................................... 5-1
5.2.1 The Burst Cycle .........................................................................................................5-1
5.2.2 The KEN# Input .........................................................................................................5-2
5.2.3 Bus Characteristics....................................................................................................5-4
5.2.4 Improving Write Cycle Latency ..................................................................................5-5
5.2.4.1 Interleaving............................................................................................................5-5
5.2.4.2 Write Posting.........................................................................................................5-5
5.2.5 Second-Level Cache..................................................................................................5-6
CHAPTER 6
CACHE SUBSYSTEM
6.1 INTRODUCTION ........................................................................................................... 6-1
6.2 CACHE MEMORY ......................................................................................................... 6-1
6.2.1 What is a Cache?.......................................................................................................6-1
6.2.2 Why Add an External Cache?....................................................................................6-2
6.3 CACHE TRADE-OFFS .................................................................................................. 6-2
6.3.1 Cache Size and Performance ....................................................................................6-3
6.3.2 Associativity and Performance Issues .......................................................................6-5
6.3.3 Block/Line Size ........................................................................................................6-10
6.3.4 Replacement Policy .................................................................................................6-11
6.4 UPDATING MAIN MEMORY ....................................................................................... 6-11
6.4.1 Write-Through and Buffered Write-Through Systems..............................................6-12
6.4.2 Write-Back System ..................................................................................................6-13
6.4.3 Cache Consistency ..................................................................................................6-13
6.5 NON-CACHEABLE MEMORY LOCATIONS............................................................... 6-15
6.6 CACHE AND DMA OPERATIONS .............................................................................. 6-16
6.7 CACHE FOR SINGLE VERSUS MULTIPLE PROCESSOR SYSTEMS..................... 6-16
6.7.1 Cache in Single Processor Systems........................................................................6-16
6.7.2 Cache in Multiple Processor Systems......................................................................6-16
6.8 AN Intel486™ PROCESSOR SYSTEM EXAMPLE..................................................... 6-18
6.8.1 The Memory Hierarchy and Advantages of a Second-level Cache .........................6-19
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