Intel Embedded Intel486 User Manual

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CONTENTS
4.3.3.2 Non-Burst Cacheable Cycles..............................................................................4-23
4.3.3.3 Burst Cacheable Cycles......................................................................................4-24
4.3.3.4 Effect of Changing KEN# during a Cache Line Fill..............................................4-25
4.3.4 Burst Mode Details...................................................................................................4-26
4.3.4.1 Adding Wait States to Burst Cycles ....................................................................4-26
4.3.4.2 Burst and Cache Line Fill Order..........................................................................4-27
4.3.4.3 Interrupted Burst Cycles......................................................................................4-28
4.3.5 8- and 16-Bit Cycles.................................................................................................4-29
4.3.6 Locked Cycles..........................................................................................................4-31
4.3.7 Pseudo-Locked Cycles ............................................................................................4-32
4.3.7.1 Floating-Point Read and Write Cycles ................................................................4-33
4.3.8 Invalidate Cycles......................................................................................................4-33
4.3.8.1 Rate of Invalidate Cycles ....................................................................................4-35
4.3.8.2 Running Invalidate Cycles Concurrently with Line Fills.......................................4-35
4.3.9 Bus Hold ..................................................................................................................4-38
4.3.10 Interrupt Acknowledge .............................................................................................4-40
4.3.11 Special Bus Cycles ..................................................................................................4-41
4.3.11.1 HALT Indication Cycle.........................................................................................4-41
4.3.11.2 Shutdown Indication Cycle..................................................................................4-41
4.3.11.3 Stop Grant Indication Cycle ................................................................................4-41
4.3.12 Bus Cycle Restart ....................................................................................................4-43
4.3.13 Bus States................................................................................................................4-45
4.3.14 Floating-Point Error Handling for the IntelDX2™ and IntelDX4™ Processors.........4-46
4.3.14.1 Floating-Point Exceptions ...................................................................................4-46
4.3.15 IntelDX2™ and IntelDX4™ Processors Floating-Point Error Handling
in AT-Compatible Systems.......................................................................................4-47
4.4 ENHANCED BUS MODE OPERATION (WRITE-BACK MODE)
FOR THE WRITE-BACK ENHANCED IntelDX4™ PROCESSOR4-50
4.4.1 Summary of Bus Differences ...................................................................................4-50
4.4.2 Burst Cycles.............................................................................................................4-50
4.4.2.1 Non-Cacheable Burst Operation.........................................................................4-51
4.4.2.2 Burst Cycle Signal Protocol.................................................................................4-51
4.4.3 Cache Consistency Cycles ......................................................................................4-52
4.4.3.1 Snoop Collision with a Current Cache Line Operation........................................4-54
4.4.3.2 Snoop under AHOLD ..........................................................................................4-54
4.4.3.3 Snoop During Replacement Write-Back..............................................................4-59
4.4.3.4 Snoop under BOFF#...........................................................................................4-61
4.4.3.5 Snoop under HOLD.............................................................................................4-64
4.4.3.6 Snoop under HOLD during Replacement Write-Back.........................................4-66
4.4.4 Locked Cycles..........................................................................................................4-67
4.4.4.1 Snoop/Lock Collision...........................................................................................4-68
4.4.5 Flush Operation .......................................................................................................4-69
4.4.6 Pseudo Locked Cycles ............................................................................................4-70
4.4.6.1 Snoop under AHOLD during Pseudo-Locked Cycles..........................................4-70
4.4.6.2 Snoop under Hold during Pseudo-Locked Cycles...............................................4-71
4.4.6.3 Snoop under BOFF# Overlaying a Pseudo-Locked Cycle..................................4-72

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English