Intel Embedded Intel486

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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CHAPTER 3
INTERNAL ARCHITECTURE
3.1 INSTRUCTION PIPELINING......................................................................................... 3-6
3.2 BUS INTERFACE UNIT................................................................................................. 3-7
3.2.1 Data Transfers ...........................................................................................................3-8
3.2.2 Write Buffers ..............................................................................................................3-8
3.2.3 Locked Cycles............................................................................................................3-9
3.2.4 I/O Transfers..............................................................................................................3-9
3.3 CACHE UNIT............................................................................................................... 3-10
3.3.1 Cache Structure .......................................................................................................3-10
3.3.2 Cache Updating .......................................................................................................3-12
3.3.3 Cache Replacement ................................................................................................3-12
3.3.4 Cache Configuration ................................................................................................3-12
3.4 INSTRUCTION PREFETCH UNIT............................................................................... 3-13
3.5 INSTRUCTION DECODE UNIT................................................................................... 3-14
3.6 CONTROL UNIT.......................................................................................................... 3-14
3.7 INTEGER (DATAPATH) UNIT..................................................................................... 3-14
3.8 FLOATING-POINT UNIT ............................................................................................. 3-15
3.8.1 IntelDX2™ and IntelDX4™ Processor On-Chip Floating-Point Unit ........................3-15
3.9 SEGMENTATION UNIT............................................................................................... 3-15
3.10 PAGING UNIT ............................................................................................................. 3-16
CHAPTER 4
BUS OPERATION
4.1 DATA TRANSFER MECHANISM.................................................................................. 4-1
4.1.1 Memory and I/O Spaces ............................................................................................4-1
4.1.1.1 Memory and I/O Space Organization....................................................................4-2
4.1.2 Dynamic Data Bus Sizing ..........................................................................................4-3
4.1.3 Interfacing with 8-, 16-, and 32-Bit Memories ............................................................4-5
4.1.4 Dynamic Bus Sizing During Cache Line Fills.............................................................4-9
4.1.5 Operand Alignment ..................................................................................................4-10
4.2 BUS ARBITRATION LOGIC ........................................................................................ 4-12
4.3 BUS FUNCTIONAL DESCRIPTION............................................................................ 4-15
4.3.1 Non-Cacheable Non-Burst Single Cycle..................................................................4-16
4.3.1.1 No Wait States ....................................................................................................4-16
4.3.1.2 Inserting Wait States...........................................................................................4-17
4.3.2 Multiple and Burst Cycle Bus Transfers...................................................................4-17
4.3.2.1 Burst Cycles ........................................................................................................4-18
4.3.2.2 Terminating Multiple and Burst Cycle Transfers .................................................4-19
4.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers.........................................4-19
4.3.2.4 Non-Cacheable Burst Cycles ..............................................................................4-20
4.3.3 Cacheable Cycles ....................................................................................................4-21
4.3.3.1 Byte Enables during a Cache Line Fill ................................................................4-22