6-17
CACHE SUBSYSTEM
idation cycle must be generated by asserting AHOLD and EADS# to the second processor and
its cache. This type of invalidation is true for the write-through cache such as the one shown in
Figure 6-10. If the caches are write-back caches the invalidation protocol may be different.
Figure 6-10. Intel486™ Processor System Arbitration
Memory bus utilization in multiple CPU systems may be the most important performance con-
sideration. In this type of system, a cache should have a very high hit rate for both reads and
writes. Accesses to main, shared memory must be minimized. Write-back cache is best-suited for
Arbitration Logic
DMA
Intel486™
Processor 1
Intel486™
Processor 0
BREQ 2 BACK 2
BREQ 0 BREQ 1
HRQ 1
HLDA 1
HRQ 0
HLDA 0
HRQ 2
HLDA 2
DREQ
DACK
L2 Cache
L2 Cache
Address
Data
Control
MemoryI/O
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