EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
7-2
Figure 7-1. Mapping Scheme
I/O mapping and memory-mapping differ in the following respects:
• The address decoding required to generate chip selects for the I/O-mapped devices is much
simpler than that required for memory-mapped devices. I/O-mapped devices reside within
the I/O space of the Intel486 processor (64 Kbytes); memory-mapped devices reside in a
much larger Intel486 processor memory space (4-gigabytes), which requires more address
lines to decode.
• The I/O space is 64 Kbytes and can be divided into 64 K of 8-bit ports, 32 K of 16-bit ports,
16 K of 32-bit ports or any combinations of ports which add up to less than 64 Kbytes. The
64 Kbytes of I/O address space refers to physical memory because I/O instructions do not
utilize the segmentation or paging hardware and are directly addressable using DX
registers.
• Memory-mapped devices can be accessed using the Intel486 processor’s instructions, so
that I/O to memory, memory-to-I/O, and I/O-to-I/O transfers, as well as compare and test
operations, can be coded efficiently.
• The I/O-mapped device can be accessed only with IN, OUT, INS, and OUTS instructions.
I/O instruction execution is synchronized with external bus activity. All I/O transfers are
performed using the AL (8-bit), AX (16-bit), or EAX (32-bit) registers.
Physical
Memory
Not
Accessible
Not
Accessible
64 Kbyte
FFFFFFFFH
00000000H
0000FFFFH
00000000H
Accessible
Programmed
I/O Space
I/O Space
Physical Memory
Space
4Gbyte
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