Intel Embedded Intel486

7-25
PERIPHERAL SUBSYSTEM
In Figure 7-11, address lines A15–A8 are ignored to maintain simplicity. Lines A7–A2 are de-
coded to generate addresses XXE0–XXFC. When a valid cycle begins, ADS# is latched in the
flip-flop.
Figure 7-12. Internal Logic and Truth Table of 74S138
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Data
Outputs
(6)
(4)
(5)
G1
G2A#
G2B#
Enable
Inputs
(1)
(2)
(3)
A
B
C
Select
Inputs
Function Table
Inputs
Outputs
Enable Select
G1 G2#
†
C B A Y0Y1Y2Y3Y4Y5Y6Y7
X1XXX11111111
0 XXXX11111111
1 000001111111
1 000110111111
1 001011011111
1 001111101111
1 010011110111
1 010111111011
1 011011111101
1 011111111110
†
G2# = G2A# + G2B#
1 = High 0= Low Level
X = Don’t Care