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PERIPHERAL SUBSYSTEM
• Industry-Standard Network Support
— IEEE 802.3 (Ethernet, Ethernet Twisted Pair, Cheapernet, StarLAN, etc.)
— IBM PC Network (baseband and broadband)
— Proprietary CSMA/CD networks up to 20 Mbits/second
— HDLC frame delimiting
• Compatible Intel486 Processor Interface
— Optimized interface to the Intel486 processor bus
— Shared Intel486 processor bus signals and memory timing
— Support for Intel486 processor byte ordering
• Architectural Features
—On-chip DMA
— Bus Throttle
— 128-byte receive FIFO, 64-byte transmit FIFO
— On-chip memory management
— Network management and diagnostics
— 82586 software-compatible mode
• Performance Features
— 9.6 msec interframe spacing for back-to-back frame transmission and reception
— 80/106 Mbytes/second bus transfer rate (burst) at 25/33 MHz
— 50/66 Mbytes/second bus transfer rate (non-burst) at 25/33 MHz
Figure 7-21 is a block diagram of the 82596 coprocessor. A serial subsystem interfaces to the
physical-layer device for the network. This subsystem performs CSMA/CD media access-control
and channel-interface functions. It supports the full set of IEEE 802.3 and other industry-standard
and proprietary network functions. A parallel subsystem interfaces to the Intel486 processor. This
subsystem contains a data interface unit, a bus interface unit, a 4-channel DMA unit, and a micro-
machine command processor. A FIFO subsystem connects the serial and parallel subsystems, al-
lowing them to run asynchronously to one another through a 128-byte receive FIFO and a 64-byte
transmit FIFO.
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