EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
8-8
Figure 8-3. Block Diagram of Integrated System Peripheral (ISP)
The EISA bus buffers (EBB) are used to interconnect the host data and address buses to the EI-
SA/ISA data and address bus. The EBB integrates multiple address or data latches and buffers
that are typically used in EISA systems, and operates in various modes to support data and ad-
dress interfaces. It has a 32-bit mode without parity and a 32-bit data mode with parity support
Bus Interface
15 Level
Interrupt
Control
IRQ <1,3-7, 8#,
9-15>
INT
BCLK
NMI
IOCHK#
PARITY#
SPKR SLOWH#
OSC
Timer 2/Counter 2
Timer 2/Counter 0
Timer 1/Counter 2
Timer 1/Counter 1
Timer 1/Counter 0
DREQ
DACK#
MREQ#
MACK#
REFRESH#
DHLDA
CPUMISS#
DHOLD
EMSTR16#
EXMASTER#
System
Arbiter
Logic
AEN#
RST
GT16M#
EOP
IRQ0
CLK
NMI
Logic
DMA
Controller
and
Refresh
Generator
START#
CMD#
HW/R#
BE3#–BE0#
DRDY
HA31#–HA2#
ST3–ST0
GT1M#
D7–D0
CSOUT#
RTCALE
RSTDRV
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