Intel Embedded Intel486 User Manual

8-23
SYSTEM BUS DESIGN
board controller. Edge/level interrupts and interrupt steering are supported for PCI plug-and-play
compatibility. The ISA bridge integrates the ISA address and data path, reducing TTL and system
cost. In addition, the integration of system clock generation logic eliminates the need for external
host and PCI clock drivers.
Figure 8-7. ISA Bridge Block Diagram
A17–A2
CMDV#
SIDLE#
LREQ#
LGNT#
SMI#
STPCLK#
EXTSMI#
CLK2IN
CLK2OUT
HCKLOUT2–HCKLOUT1
SYSCLK
PCICLK2–PCICLK1
XBUSTR#
XBUSOE#
BIOSCS#
KBCCS#
RTCCS#
RTCALE
FERR#
IGNNE#
OSC
SPKR
IOCS16#
MEMCS16#
ZEROWS#
MEMR#
MEMW#
SMEMR#
SMEMW#
IOCHRDY
BALE
IOR#
SERR#
DREQ7–DREQ5
DACK7–DACK5
TC
REFRESH#
IRQ8#
IRQ(15,14,11:9,7:3,1)
IRQ12/M
INTR
PIRQ0#
PIRQ1#
TESTIN#
CPURST
RSTDRV
PCIRST
PWROK#
SRESET
IOW#
LA23–LA17
SA19–SA0
SD15–SD0
SBHE#
HCLKIN
AEN
IOCHK#
NMI
DREQ3–DREQ0
DACK3–DACK0
PCI
Link
Interface
SMM
Interface
Clock
Interface
Reset
Interface
X-Bus
Interface
Timers/
Counters
1x82C54
ISA Bus
Interface
NMI
Interface
DMA
2x82C37
Interrupt
2x82C59
Test
ISA Bridge

Intel Embedded Intel486 Specifications

General

Brand	Intel
Model	Embedded Intel486
Category	Computer Hardware
Language	English