EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10-40
on-chip registers, an instruction execution breakpoint can be placed in ROM code or in code
shared by several tasks. Neither of these is supported by the INT3 breakpoint opcode.
The debug register provides the ability to specify four distinct breakpoint addresses, control op-
tions, and read breakpoint status. When the CPU goes through reset, the breakpoints are all in the
disabled state. Hence the breakpoints cannot occur unless the debug resisters are programmed.
It is possible to specify up to four breakpoint addresses by writing into debug registers. The debug
registers are shown in Figure 10-31. The addresses specified are 32-bit linear addresses. The pro-
cessor hardware continuously compares the linear breakpoint addresses in DR3–DR0 with the
linear addresses generated by executing software. When the paging is disabled then the linear ad-
dress is equal to the physical address. If the paging is enabled then the linear address is translated
to a 32-bit address by the on-chip paging unit. Whether paging is enabled or disabled, the break-
point register holds linear addresses.
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