Index-1
INDEX
#, defined, 1-3
16-bit bus cycles, 4-29
16-bit I/O interface, 7-10 to 7-12
16-bit memories, 4-3
2-2 cycles, 7-22
32-bit I/O interface, 7-14 to 7-16
32-bit memories, 4-3
386
see Intel386 processor
485Turbocache module,
9-12
486
see Intel486 processor
82357 integrated system peripheral (ISP),
8-7
82420EX PCIset
block diagram,
8-20
DMA controller, 8-33
host interface, 8-24
IB component, 8-22
ISA interface, 8-30
82557 LAN controller
block diagram,
7-52
bus operation, 7-52
control, 7-53
features, 7-51
initializing, 7-52
overview, 7-50
PCI bus interface, 7-52
82596CA coprocessor, 7-38 to 7-41
interfacing to Intel486 processor, 7-44 to 7-45
memory structure, 7-46
performance issues, 7-49
signals, 7-42
82C59A programmable interrupt
controller,
7-35 to 7-36
8-bit bus cycles, 4-29
8-bit I/O interface, 7-7 to 7-9
8-bit memories, 4-3
A
A.C. termination, 10-21
Active termination, 10-22
Address bus
interface to I/O devices,
7-6
Address decoding, 7-23
for I/O devices, 7-5
Address signals, 4-1
ALU, 3-14
Applications of the Intel486 processor, 2-11
Assert, defined, 1-4
B
Block diagrams
82420EX PCIset,
8-20
82557 LAN Controller, 7-52
lntel486 SX processor, 3-3
lntelDX2 and IntelDX4 processors, 3-2
peripheral subsystem example, 7-17
ULP lntel486 SX and ULP Intel486 GX
processors,
3-4
Block size, in cache, 6-10
Breakpoint instruction, 10-39
Broadcasting cache data, 6-14
Burst cycles, 4-50 to 4-52
access lengths of CPU functions, 5-2
memory logic and, 5-1
typical cycle, 5-3
writes, 5-2
Burst mode, 4-26 to 4-29
wait states in, 9-9
Bus arbitration
in a multi-processor system,
4-14 to 4-15
in a single-processor system, 4-12 to 4-13
Bus contention, 7-26
Bus control logic, 7-20 to 7-23
Bus control signals, 7-21 to 7-22
Bus cycles
access length,
5-2
mix of, with cache, 9-6
Bus hold, 4-38
Bus interface unit, 3-7 to 3-8
Bus masters, multiple, 4-14
Bus throttle timers, 82596CA coprocessor, 7-49
Bus, see Processor bus or System bus
Byte enables,
4-1
Byte swapping, 4-8
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