EasyManua.ls Logo

Intel Embedded Intel486 - Page 330

Intel Embedded Intel486
334 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Index-2
C
Cache
see also Level-1 cache or Second-level cache
4-way set associative,
6-9
block size, 6-10
broadcasting, 6-14
configuration options, 3-13
consistency, 4-52, 6-13, 7-28
defined, 6-1
direct mapped, 6-6
effect on bus cycles, 9-6
external
see Second-level cache
fully associative,
6-5
hardware transparency, 6-14
hit rates (L1), 6-3, 9-6
invalidating lines, 3-12
memory hierarchy and, 6-19
memory mapped I/O devices, 7-27
multi-processor systems, 6-16
non-cacheable regions, 3-12
on-chip, 2-6, 3-4, 7-28, 9-4
organization on-chip, 3-11, 9-4
performance issues, 6-2 to 6-5, 9-4
replacement, 3-12, 6-11
sector buffering, 6-9
set associative, 6-8
single vs. multiple processor systems, 6-16
structure, 3-10
two-way set associative, 6-8
updating, 3-12
updating main memory, 6-11
write-back, 3-12, 6-13
write-through, 3-12, 6-12
Cache enable (KEN#) signal, 5-2 to 5-4
Cache transparency, 6-16
Cache unit, 3-10
Cacheable cycles, 4-21, 5-2 to 5-4
Chapter summaries, 1-1
Chip capacitors, decoupling, 10-8
CHMOS IV process, 10-1
Clear, defined, 1-4
Clock (CLK) signal
skew,
10-30
Clock considerations, 10-30 to 10-32
Clock routing, 10-32
Clock timings, 10-31
Control registers
debug,
10-42
Control unit, 3-14
Controllers, embedded, 2-12
Cross-talk, 10-25
Customer service, 1-5
D
Daisy chaining, 10-24
Data access rate, 5-1
Data buffers, 7-32
Data bus
dynamic bus sizing,
2-1, 4-3
Data transceivers, 7-26
Data transfer, 3-8, 4-1
Datapath unit, 3-14
Deassert, defined, 1-4
Debug control register, 10-42
Debug registers, 10-39 to 10-41
Debugging, 10-37, 10-43
features of the Intel486 processor, 10-39
Decoupling capacitors, 10-6
Derating curve, 10-36
Direct mapped cache, 6-6
DMA
cache and,
6-16
in multiple processor system, 4-14 to 4-15
in single processor system, 4-12 to 4-13
DMA controller
82420EX PCIset,
8-33
in EISA designs, 8-16
Documents, related, 1-6
DOS address, defined, 1-4
DRAM
clock latencies,
5-6
design, 9-14
interleaving, 9-14
Dynamic data bus sizing, 2-1, 4-3, 7-3

Table of Contents

Related product manuals