Intel Embedded Intel486 - Page 331

Index-3
INDEX
E
EBC host bus interface, 8-9 to 8-11
EDO DRAM, 9-14
EISA
bus buffers (EBB),
8-8
bus controller, 8-6
bus interface to the EBC, 8-11 to 8-13
overview, 8-2
Electromagnetic interference, 10-25
Electrostatic interference, 10-28
Embedded controllers, 2-12
Embedded personal computers, 2-12
Enhanced bus mode features, 2-3, 4-50
Expanded address, defined, 1-4
External cache
see Second-level cache
F
FaxBack service, 1-5
Features
debugging,
10-39
enhanced bus mode, 2-3
Intel486 processor, 2-2 to 2-3
SL technology, 2-3
Floating-point cycles, 4-33
Floating-point error handling, 4-46
Floating-point unit
overview,
2-6, 3-15
performance considerations, 9-16
Flush cycles, 4-69
Fully associative cache, 6-5
Functional units, 3-1
bus interface, 3-7 to 3-8
cache, 3-10
control, 3-14
datapath, 3-14
floating-point, 3-15
instruction decode, 3-14
instruction prefetch, 3-13
integer (datapath), 3-14
memory management, 3-5
paging, 3-16
segmentation, 3-15
G
General-purpose registers, 3-14
Ground planes, 10-2 to 10-3
double layer boards, 10-3 to 10-5
H
HALT cycle, 4-41
Hardware transparency, with cache, 6-14
Heatsink, 10-34 to 10-36
I
I/O cycles, 7-27
I/O devices
address decoding,
7-5
non-cacheable, 7-27
I/O interface
16-bit,
7-10 to 7-12
32-bit, 7-14 to 7-16
8-bit, 7-7 to 7-9
I/O mapping vs. memory-mapping, 7-2
I/O memory space, 4-1
I/O transfers, 3-9
Impedance, 10-3
matching, 10-18, 10-23
mismatch, 10-12
Instruction decode unit, 3-14
Instruction execution performance, 9-2
Instruction pipelining, 3-6
Instruction prefetch unit, 3-13
Instructions, notational conventions, 1-3
Integer (datapath) unit, 3-14
Intel386 processor
bus cycle mix,
5-5
differences with Intel486
processor,
7-33 to 7-34