EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Index-4
Intel486 processor
debugging,
10-37
differences with Intel386
processor,
7-33 to 7-34
execution times, 9-2
features, 2-2 to 2-3
functional units, 3-1
instruction mix, 9-3
interfacing to 8042 devices, 7-34
overview of embedded processors, 2-1
product options, 2-4
thermal characteristics, 10-33
Interference, 10-25
electromagnetic, 10-25
electrostatic, 10-28
Interleaving, 9-14
Internal cache
see Level-1 cache or Cache,
6-19
Interrupt acknowledge cycles, 4-40
Interrupt controllers
82C59A,
7-35 to 7-36
cascaded, 7-37 to 7-38
single, 7-35
Interrupts
handling more than 64,
7-38
Invalidate cycles, 4-33 to 4-37
ISA bus, interface signals with EBC, 8-12
ISP
functions of,
8-16
interface to EISA system bus, 8-17
interface to host, 8-17
interface wit EBC, 8-13
K
KEN#, 5-2
L
L2 cache
see Second-level cache
LAN controller
82596CA,
7-38
Latches, 7-32
Latch-up, 10-30
Lattice diagram, 10-16
Leaded capacitors, decoupling, 10-9
Level-1 cache
see also Cache
hit rates,
6-3
Line size, in cache, 6-10
Literature, 1-6
Literature, ordering, 1-6, 1-7
Locked cycles, 3-9, 4-31
Loosely coupled multiprocessor system, 2-9
LRU cache replacement, 3-12
M
Machine status register, 3-12, 4-47
Manual contents, 1-1
Measurements, defined, 1-3
Media access through 82596CA
coprocessor,
7-46
Memory
16-bit,
4-3
8-bit, 4-3
external, 9-8
I/O space and, 4-2
management, 2-5
mapping techniques, 7-1
non-cacheable, 6-15
performance, 9-1, 9-8
updating from cache, 6-11
Memory management unit, 3-5
Micro strip lines, 10-10
Multiple bus masters, 4-14
Multiprocessor system, 2-9
N
Non-cacheable memory, 6-15
Notational conventions, 1-3
O
On-chip cache, 2-6
see also Cache
performance,
9-5
On-chip floating-point unit, 3-15
Operating modes, 2-5
Overlapping write cycles, 5-5
Overshoot, 10-13
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