Index-5
INDEX
P
Page tables, 3-16
Paging unit, 3-5, 3-16
Paging, overview, 2-5
Parallel termination, 10-19
PC/AT address, defined, 1-4
PCI
example of system design,
8-19 to 8-34
interface to the 82557, 7-52
overview of architecture, 8-19
Peripheral subsystem, components of, 7-17
Personal computers, embedded, 2-12
Posted write
circuit timings,
7-32
cycles, 9-15
Power dissipation, 10-1
Power management features, 2-1
Processor bus
basic 2-2 cycle,
4-16
basic 3-3 cycle, 4-17
burst cycles, 4-17
cacheable cycles, 4-21
features, 5-1
restart cycles, 4-43
snooping, 6-14
Product family, 2-4
Propagation delay, 10-29
Protected mode, 2-5, 3-6
Pseudo locked cycles, 4-70 to 4-73
Pseudo-LRU, 3-12
R
Read cycles
timing,
7-29 to 7-30
Real mode, 2-5, 3-6
Reflection voltage, 10-14
Registers
CR0,
4-22, 4-46
CR3, 3-17
debug, 10-39 to 10-41
general purpose, 3-14
machine status, 3-12, 4-47
notational conventions, 1-4
Related documents, 1-6
Restart cycles, 4-43
S
Second-level cache, 2-10, 5-6
memory hierarchy, 6-19
overview, 6-16 to 6-18
see also Cache
Sector buffering cache,
6-9
Segmentation unit, 3-5, 3-15
Segmentation, overview, 2-5
Series termination, 10-18
Set associative cache, 6-8
Set, defined, 1-4
Shutdown indication cycle, 4-41
Signals
82596CA coprocessor,
7-42
address, 3-8, 4-1
bus control, 7-21 to 7-22
byte enables, 4-1
Cache Enable (KEN#), 5-2
KEN#, 5-2
notational conventions, 1-4
SMI#, 2-3
UP#, 2-7
wait state generation, 7-22
Single processor system, 2-8 to 2-9
SL technology, 2-1, 2-3
Snoop cycles, 4-52 to 4-73, 6-14
Star connection, 10-32
Stop grant bus cycle, 4-42
Strip lines, 10-11
Sub-block cache, 6-9
System architecture overview, 2-7 to 2-8
System Management Mode, 3-6
T
Technical support, 1-5
Terminology, 1-4
Thermal characteristics, 10-33
Thevenins equivalent circuit, 10-20
Translation lookaside buffer (TLB), 3-16 to 3-17
Transmission lines
loaded,
10-13
micro strip, 10-10
strip, 10-11
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