Function library
Function blocks
9.2.63 Storage block (STORE)
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EDSVS9332S-D11 EN 3.0
9.2.63.2 Storing STORE1 phase signal
A phase signal is created from a speed signal at STORE1-IN. The following sequence shows, in
addition to storing, the options of signal output
z The actual phase signal is output at STORE1-ACT.
1. A LOW-HIGH edge at the TP input E5 stores the last phase signal and outputs it at
STORE1-PH1.
2. STORE1-ENTP = LOW-HIGH edge enables the TP input E5 for the next triggering.
3. A renewed LOW-HIGH edge at the TP input E5 stores the last phase signal.
– STORE1-PH1 outputs this last phase signal.
– STORE1-PH2 outputs the last but one phase signal.
– STORE1-PHDIFF outputs the difference of STORE1-PH1 and STORE1-PH2.
z STORE1-RESET = HIGH resets memory, counter and integrators and activates the TP input
for triggering.
Output of the difference between both phase signals stored
z A two-stage counter controls the output to STORE1-PHDIFF.
z Every second triggering via the TP input results in a new output to STORE1-PHDIFF.
z STORE1-LOAD0 = HIGH resets the counter.
Additional control
1. STORE1-LOAD1 = LOW-HIGH edge, sets the counter to the first stage (preparation for the
output to STORE1-PHDIFF).
2. Triggering via TP input E5 sets the counter to the second stage (output to STORE1-PHDIFF is
done).
Tip!
If STORE1-LOAD1 is set cyclically, STORE1-PHDIFF outputs a new difference signal after every
triggering.
9.2.63.3 Storing STORE2 phase signal
A phase signal is created from a speed signal at MCTRL-PHI-ACT. The following sequence shows,
in addition to storing, the options of signal output.
z The actual phase signal is output to STORE2-ACT.
1. A LOW-HIGH edge at the TP input E4 stores the last phase signal and outputs it at
STORE2-PH1.
2. STORE2-ENTP = LOW-HIGH edge activates the TP input E4 for the next triggering.
3. A renewed LOW-HIGH edge at the TP input E4 stores the last phase signal.
– STORE2-PH1 outputs this last phase signal.
– STORE2-PH2 outputs the last but one phase signal.
z STORE2-RESET = HIGH resets the memory and integrator and activates the TP input E4 for
triggering.
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