NXP Semiconductors MKL25Z128VLK4 - Clock Definitions

32 kHz IRC
PLL
FLL
MCGOUTCLK
MCGPLLCLK
MCG
MCGFLLCLK
OUTDIV1
Core clock,
platform clock,
and system clock
4 MHz IRC
OUTDIV4
Flash clock
Bus clock/
EXTAL0
XTAL0
System oscillator
SIM
FRDIV
MCGIRCLK
ERCLK32K
OSC32KCLK
XTAL_CLK
OSCERCLK
OSC
logic
Clock options for some
peripherals (see note)
Clock options for
some peripherals
(see note)
MCGFLLCLK
MCGPLLCLK/
Note: See subsequent sections for details on where these clocks are used.
PMC logic
PMC
LPO
OSCCLK
CG
CG
CG
CG
CG — Clock gate
÷2
RTC_CLKOUT
RTC
Counter logic
1Hz
RTC_CLKIN
FCRDIV
Figure 5-1. Clocking diagram
5.4 Clock definitions
The following table describes the clocks in the previous block diagram.
Clock name Description
Core clock MCGOUTCLK divided by OUTDIV1, clocks the ARM Cortex-
M0+ core
Platform clock MCGOUTCLK divided by OUTDIV1, clocks the crossbar
switch and NVIC
System clock MCGOUTCLK divided by OUTDIV1, clocks the bus masters
directly
Bus clock System clock divided by OUTDIV4, clocks the bus slaves and
peripherals.
Table continues on the next page...
Clock definitions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
116 Freescale Semiconductor, Inc.