UARTx_C2 field descriptions
Field Description
7
TIE
Transmit Interrupt Enable for TDRE
0 Hardware interrupts from TDRE disabled; use polling.
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable for TC
0 Hardware interrupts from TC disabled; use polling.
1 Hardware interrupt requested when TC flag is 1.
5
RIE
Receiver Interrupt Enable for RDRF
0 Hardware interrupts from RDRF disabled; use polling.
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable for IDLE
0 Hardware interrupts from IDLE disabled; use polling.
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
TE must be 1 to use the UART transmitter. When TE is set, the UART forces the TxD pin to act as an
output for the UART system.
When the UART is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the
direction of traffic on the single UART communication line (TxD pin).
TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or
queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
0 Transmitter off.
1 Transmitter on.
2
RE
Receiver Enable
When the UART receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS is
set the RxD pin reverts to being a general-purpose I/O pin even if RE is set.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control
This bit can be written to 1 to place the UART receiver in a standby state where it waits for automatic
hardware detection of a selected wakeup condition. The wakeup condition is an idle line between
messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE =
1, address-mark wakeup. Application software sets RWU and, normally, a selected hardware condition
automatically clears RWU.
0 Normal UART receiver operation.
1 UART receiver in standby waiting for wakeup condition.
0
SBK
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 or 12, 13 or 14 or 15 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is
set. Depending on the timing of the set and clear of SBK relative to the information currently being
transmitted, a second break character may be queued before software clears SBK.
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
754 Freescale Semiconductor, Inc.
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