NXP Semiconductors MKL25Z128VLK4 - UART Match Address Registers 2 (Uartx_Ma2)

39.2.10 UART Match Address Registers 2 (UARTx_MA2)
The MA1 and MA2 registers are compared to input data addresses when the most
significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the
following data is transferred to the data register. If a match fails, the following data is
discarded. Software should only write a MA register when the associated C4[MAEN] bit
is clear.
Address: Base address + 9h offset
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_MA2 field descriptions
Field Description
7–0
MA
Match Address
39.2.11 UART Control Register 4 (UARTx_C4)
Address: Base address + Ah offset
Bit 7 6 5 4 3 2 1 0
Read
MAEN1 MAEN2 M10 OSR
Write
Reset
0 0 0 0 1 1 1 1
UARTx_C4 field descriptions
Field Description
7
MAEN1
Match Address Mode Enable 1
Refer to Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.
6
MAEN2
Match Address Mode Enable 2
Refer to Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.
Table continues on the next page...
Register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
736 Freescale Semiconductor, Inc.