3.7.2 CMP Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
CMP
Peripheral
bridge 0
Other peripherals
Figure 3-22. CMP configuration
Table 3-33. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP Instantiation Information
The device includes one high speed comparator and two 8-input multiplexors for both the
inverting and non-inverting inputs of the comparator. Each CMP input channel connects
to both muxes. Two of the channels are connected to internal sources, leaving resources
to support up to 6 input pins. See the channel assignment table for a summary of CMP
input connections for this device.
The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which
provides a selectable voltage reference for applications where voltage reference is needed
for internal connection to the CMP.
The CMP can be optionally on in all modes except VLLS0.
The CMP has several module to module interconnects in order to facilitate ADC
triggering, TPM triggering and UART IR interfaces. For complete details on the CMP
module interconnects please refer to the Module-to-Module section.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 81
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