NXP Semiconductors MKL25Z128VLK4 - Flash Configuration Register 1 (SIM_FCFG1); KL25 Sub-Family Reference Manual, Rev. 3, September

SIM_CLKDIV1 field descriptions (continued)
Field Description
18–16
OUTDIV4
Clock 4 output divider value
This field sets the divide value for the bus and flash clock and is in addition to the System clock divide
ratio. At the end of reset, it is loaded with 0001 (divide by two).
000 Divide-by-1.
001 Divide-by-2.
010 Divide-by-3.
011 Divide-by-4.
100 Divide-by-5.
101 Divide-by-6.
110 Divide-by-7.
111 Divide-by-8.
15–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)
Address: 4004_7000h base + 104Ch offset = 4004_804Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 PFSIZE 0
W
Reset
0 0 0 0 * * * * 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FLASHDOZE
FLASHDIS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
* Notes:
PFSIZE field: Device specific value.•
Chapter 12 System integration module (SIM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 211