NXP Semiconductors MKL25Z128VLK4 - Freescale Semiconductor, Inc

of the slave. The next SPSCK edge causes both the master and the slave to sample the
data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge,
the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and
MISO outputs of the master and slave, respectively.
When CPHA = 1, the slave's SS input is not required to go to its inactive high level
between transfers. In this clock format, a back-to-back transmission can occur, as
follows:
1. A transmission is in progress.
2. A new data byte is written to the transmit buffer before the in-progress transmission
is complete.
3. When the in-progress transmission is complete, the new, ready data byte is
transmitted immediately.
Between these two successive transmissions, no pause is inserted; the SS pin remains
low.
The following figure shows the clock formats when CPHA = 0. At the top of the figure,
the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS
IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines
show the order of SPI data bits depending on the setting in LSBFE. Both variations of
SPSCK polarity are shown, but only one of these waveforms applies for a specific
transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the
MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the
MOSI output pin from a master and the MISO waveform applies to the MISO output
from a slave. The SS OUT waveform applies to the slave select output from a master
(provided MODFEN and SSOE = 1). The master SS output goes to active low at the start
of the first bit time of the transfer and goes back high one-half SPSCK cycle after the end
of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input
of a slave.
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 675