12.2.18 COP Control Register (SIM_COPC)
All of the bits in this register can be written only once after a reset.
Address: 4004_7000h base + 1100h offset = 4004_8100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
COPT
COPCLKS
COPW
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
SIM_COPC field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–2
COPT
COP Watchdog Timeout
These write-once bits select the timeout period of the COP. The COPT field along with the COPCLKS bit
define the COP timeout period.
00 COP disabled
01 COP timeout after 2
5
LPO cycles or 2
13
bus clock cycles
10 COP timeout after 2
8
LPO cycles or 2
16
bus clock cycles
11 COP timeout after 2
10
LPO cycles or 2
18
bus clock cycles
1
COPCLKS
COP Clock Select
This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP
1 Bus clock is source to COP
0
COPW
COP windowed mode
Windowed mode is only supported when COP is running from the bus clock. The COP window is opened
three quarters through the timeout period.
0 Normal mode
1 Windowed mode
Chapter 12 System integration module (SIM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 215
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