NXP Semiconductors MKL25Z128VLK4 - Functional Description

38.4 Functional description
This section provides a comprehensive functional description of the I2C module.
38.4.1 I2C protocol
The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to it must have open drain or open collector outputs. A
logic AND function is exercised on both lines with external pull-up resistors. The value
of these resistors depends on the system.
Normally, a standard instance of communication is composed of four parts:
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The following
figure illustrates I2C bus system communication.
S C L
S D A
D 0
D a ta B y t e
N e w C a llin g A d d r e s s
X X
W r ite
C a llin g A d d r e s s
W r ite
W r ite
S D A
C a llin g A d d r e s s R e a d /
X X X D 7 D 6 D 5 D 4 D 3 D 2 D 1A D 6 A D 5A D 7 A D 4
L S B
M S B
1
6
2
5
8
3
4
7
9
1
6
2
5
8
3
4
7
9
L S B
M S B
1
6
2
5
8
3
4
7
9
L S B
M S B
1
6
2
5
8
3
4
7
9
L S B
M S B
A D 6 R /WA D 3 A D 2 A D 1A D 5A D 7 A D 4 A D 6 R /WA D 3 A D 2 A D 1A D 5A D 7 A D 4
R e a d /
R e a d /
R / WA D 3 A D 2 A D 1
SCL
Start Signal
Ack
Bit
No
Ack
Bit
Stop
Signal
Start
Signal
Ack
Bit
Repeated
Start
Signal
No
Ack
Bit
Stop
Signal
Figure 38-38. I2C bus transmission signals
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
702 Freescale Semiconductor, Inc.