NXP Semiconductors MKL25Z128VLK4 - SPI Data Register (Spix_D)

37.3.5 SPI data register (SPIx_D)
This register is both the input and output register for SPI data. A write to the register
writes to the transmit data buffer, allowing data to be queued and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is
transmitted immediately after the previous transmission has completed.
The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept
new data. When the transmit DMA request is disabled (TXDMAE is 0): The S register
must be read when SPTEF is set before writing to the SPI data register; otherwise, the
write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when
SPTEF is set, the SPI data register can be written automatically by DMA without reading
the S register first.
Data may be read from the SPI data register any time after SPRF is set and before another
transfer is finished. Failure to read the data out of the receive data buffer before a new
transfer ends causes a receive overrun condition, and the data from the new transfer is
lost. The new data is lost because the receive buffer still held the previous character and
was not ready to accept the new data. There is no indication for a receive overrun
condition, so the application system designer must ensure that previous data has been
read from the receive buffer before a new transfer is initiated.
Address: 4007_6000h base + 5h offset = 4007_6005h
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI0_D field descriptions
Field Description
7–0
Bits[7:0]
Data (low byte)
Chapter 37 Serial Peripheral Interface (SPI)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 667