NXP Semiconductors MKL25Z128VLK4 - Reset; Low Power Modes Operation; Interrupts

25.9 Reset
There is no reset state associated with the OSC module. The counter logic is reset when
the OSC is not configured to generate clocks.
There are no sources of reset requests for the OSC module.
25.10 Low Power Modes Operation
When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and
EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low
Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and
EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still
functional in these modes. After waking up from Very Low Leakage Stop (VLLSx)
modes, all OSC register bits are reset and initialization is required through software.
25.11 Interrupts
The OSC module does not generate any interrupts.
Reset
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
414 Freescale Semiconductor, Inc.