USBx_CTL field descriptions (continued)
Field Description
3
HOSTMODEEN
When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the
USB module performs USB transactions under the programmed control of the host processor.
2
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling. This allows the
USB Module to perform remote wake-up. Software must set RESUME to 1 for the required
amount of time and then clear it to 0. If the HOSTMODEEN bit is set, the USB module appends
a Low Speed End of Packet to the Resume signaling when the RESUME bit is cleared. For
more information on RESUME signaling see Section 7.1.4.5 of the USB specification version
1.0.
1
ODDRST
Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the
EVEN BDT bank.
0
USBENSOFEN
USB Enable
Setting this bit causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit
resets much of the logic in the SIE. When host mode is enabled, clearing this bit causes the
SIE to stop sending SOF tokens.
0 Disables the USB Module.
1 Enables the USB Module.
35.4.15 Address register (USBx_ADDR)
Holds the unique USB address that the USB module decodes when in Peripheral mode
(HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB
module transmits this address with a TOKEN packet. This enables the USB module to
uniquely address an USB peripheral. In either mode, USB_EN within the control register
must be 1. The Address register is reset to 0x00 after the reset input becomes active or the
USB module decodes a USB reset signal. This action initializes the Address register to
decode address 0x00 as required by the USB specification.
Address: 4007_2000h base + 98h offset = 4007_2098h
Bit 7 6 5 4 3 2 1 0
Read
LSEN ADDR
Write
Reset
0 0 0 0 0 0 0 0
USBx_ADDR field descriptions
Field Description
7
LSEN
Low Speed Enable bit
Informs the USB module that the next token command written to the token register must be performed at
low speed. This enables the USB module to perform the necessary preamble required for low-speed data
transmissions.
6–0
ADDR
USB Address
Defines the USB address that the USB module decodes in peripheral mode, or transmits when in host
mode.
Chapter 35 Universal Serial Bus OTG Controller (USBOTG)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 635
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