NXP Semiconductors MKL25Z128VLK4 - Compute Operation Control Register (MCM_CPO)

18.2.4 Compute Operation Control Register (MCM_CPO)
This register controls the Compute Operation.
Address: F000_3000h base + 40h offset = F000_3040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CPOWOI
CPOACK
CPOREQ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_CPO field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
CPOWOI
Compute Operation wakeup on interrupt
0 No effect.
1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
1
CPOACK
Compute Operation acknowledge
0 Compute operation entry has not completed or compute operation exit has completed.
1 Compute operation entry has completed or compute operation exit has not completed.
0
CPOREQ
Compute Operation request
This bit is auto-cleared by vector fetching if CPOWOI = 1.
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Memory map/register descriptions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
296 Freescale Semiconductor, Inc.