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MCM_CPO field descriptions (continued)
Field
Description
0
Request is cleared.
1
Request Compute Operation.
Chapter 18 Miscellaneous Control Module (MCM)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc.
297
296
298
Table of Contents
Main Page
Default Chapter
3
Table of Contents
3
Chapter 1 About this Document
33
Overview
33
Purpose
33
Audience
33
Conventions
33
Numbering Systems
33
Typographic Notation
34
Special Terms
34
Chapter 2 Introduction
35
Overview
35
Kinetis L Series
35
KL25 Sub-Family Introduction
38
Module Functional Categories
39
ARM® Cortex™-M0+ Core Modules
39
System Modules
40
Memories and Memory Interfaces
41
Clocks
41
Security and Integrity Modules
42
Analog Modules
42
Timer Modules
42
Communication Interfaces
43
Human-Machine Interfaces
44
Orderable Part Numbers
44
Chapter 3 Chip Configuration
45
Introduction
45
Module to Module Interconnects
45
KL25 Sub-Family Reference Manual, Rev. 3, September
46
Analog Reference Options
48
Core Modules
48
ARM Cortex-M0+ Core Configuration
48
Nested Vectored Interrupt Controller (NVIC) Configuration
51
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
55
System Modules
56
SIM Configuration
56
System Mode Controller (SMC) Configuration
57
PMC Configuration
57
Low-Leakage Wake-Up Unit (LLWU) Configuration
58
MCM Configuration
60
Crossbar-Light Switch Configuration
61
Peripheral Bridge Configuration
62
DMA Request Multiplexer Configuration
63
DMA Controller Configuration
66
Computer Operating Properly (COP) Watchdog Configuration
67
Clock Modules
70
MCG Configuration
70
OSC Configuration
71
Memories and Memory Interfaces
72
Flash Memory Configuration
72
Flash Memory Controller Configuration
74
SRAM Configuration
75
KL25 Sub-Family Reference Manual, Rev. 3, September
75
Analog
77
16-Bit SAR ADC Configuration
77
CMP Configuration
81
12-Bit DAC Configuration
83
Timers
84
Timer/Pwm Module Configuration
84
PIT Configuration
87
Low-Power Timer Configuration
88
RTC Configuration
90
Communication Interfaces
91
Universal Serial Bus (USB) FS Subsystem
91
SPI Configuration
96
I2C Configuration
97
UART Configuration
98
Human-Machine Interfaces (HMI)
99
GPIO Configuration
99
TSI Configuration
101
Memory Map
102
Introduction
105
System Memory Map
105
Flash Memory Map
106
Chapter 4 Alternate Non-Volatile IRC User Trim Description
107
SRAM Memory Map
107
Bit Manipulation Engine
107
Peripheral Bridge (AIPS-Lite) Memory Map
108
Read-After-Write Sequence and Required Serialization of Memory Operations
108
Peripheral Bridge (AIPS-Lite) Memory Map
109
KL25 Sub-Family Reference Manual, Rev. 3, September
110
Modules Restricted Access in User Mode
112
Private Peripheral Bus (PPB) Memory Map
112
Chapter 5
115
Introduction
115
Programming Model
115
High-Level Device Clocking Diagram
115
Clock Definitions
116
Device Clock Summary
117
Internal Clocking Requirements
119
Clock Divider Values after Reset
119
VLPR Mode Clocking
120
Clock Gating
121
Module Clocks
121
PMC 1-Khz LPO Clock
122
COP Clocking
122
RTC Clocking
123
LPTMR Clocking
123
TPM Clocking
124
USB FS OTG Controller Clocking
124
UART Clocking
125
Chapter 6 Reset and Boot
127
Introduction
127
Reset
127
Power-On Reset (POR)
128
System Reset Sources
128
MCU Resets
131
Reset Pin
133
Debug Resets
133
Boot
134
Boot Sources
134
FOPT Boot Options
134
KL25 Sub-Family Reference Manual, Rev. 3, September
134
Boot Sequence
135
Chapter 7 Power Management
137
Introduction
137
Clocking Modes
137
Partial Stop
137
DMA Wakeup
138
Compute Operation
139
Peripheral Doze
140
Clock Gating
141
Power Modes
141
Entering and Exiting Power Modes
143
Module Operation in Low Power Modes
143
Chapter 8 Security
149
Introduction
149
Flash Security
149
Security Interactions with Other Modules
149
Security Interactions with Debug
150
Chapter 9 Debug
151
Introduction
151
Debug Port Pin Descriptions
151
SWD Status and Control Registers
152
MDM-AP Control Register
153
MDM-AP Status Register
154
KL25 Sub-Family Reference Manual, Rev. 3, September
156
Micro Trace Buffer (MTB)
157
Introduction
159
Chapter 10
160
Port Control and Interrupt Module Features
160
Clock Gating
161
KL25 Pinouts
164
Module Signal Description Tables
168
Core Modules
169
Analog
170
Communication Interfaces
171
Human-Machine Interfaces (HMI)
173
Introduction
175
Modes of Operation
176
External Signal Description
176
KL25 Sub-Family Reference Manual, Rev. 3, September
176
Detailed Signal Description
177
Memory Map and Register Definition
177
Pin Control Register N (Portx_Pcrn)
183
Global Pin Control Low Register (Portx_Gpclr)
185
Global Pin Control High Register (Portx_Gpchr)
186
Interrupt Status Flag Register (Portx_Isfr)
186
Functional Description
187
Pin Control
187
Global Pin Control
188
External Interrupts
188
Chapter 12 System Integration Module (SIM)
191
Introduction
191
Features
191
Memory Map and Register Definition
191
System Options Register 1 (SIM_SOPT1)
193
SOPT1 Configuration Register (SIM_SOPT1CFG)
194
System Options Register 2 (SIM_SOPT2)
195
System Options Register 4 (SIM_SOPT4)
197
System Options Register 5 (SIM_SOPT5)
199
System Options Register 7 (SIM_SOPT7)
200
System Device Identification Register (SIM_SDID)
202
System Clock Gating Control Register 4 (SIM_SCGC4)
204
System Clock Gating Control Register 5 (SIM_SCGC5)
206
System Clock Gating Control Register 6 (SIM_SCGC6)
207
System Clock Gating Control Register 7 (SIM_SCGC7)
209
System Clock Divider Register 1 (SIM_CLKDIV1)
210
Flash Configuration Register 1 (SIM_FCFG1)
211
KL25 Sub-Family Reference Manual, Rev. 3, September
211
Flash Configuration Register 2 (SIM_FCFG2)
213
Unique Identification Register MID-High (SIM_UIDMH)
213
Unique Identification Register MID Low (SIM_UIDML)
214
Unique Identification Register Low (SIM_UIDL)
214
COP Control Register (SIM_COPC)
215
Service COP Register (SIM_SRVCOP)
216
Functional Description
216
Chapter 13 System Mode Controller (SMC)
217
Introduction
217
Modes of Operation
217
Memory Map and Register Descriptions
219
Power Mode Protection Register (SMC_PMPROT)
219
Power Mode Control Register (SMC_PMCTRL)
221
Stop Control Register (SMC_STOPCTRL)
222
Power Mode Status Register (SMC_PMSTAT)
223
Functional Description
224
Power Mode Transitions
224
Power Mode Entry/Exit Sequencing
227
Run Modes
229
Wait Modes
231
Stop Modes
232
Debug in Low Power Modes
235
Chapter 14 Power Management Controller (PMC)
237
Introduction
237
Features
237
Low-Voltage Detect (LVD) System
237
LVD Reset Operation
238
LVD Interrupt Operation
238
Low-Voltage Warning (LVW) Interrupt Operation
238
KL25 Sub-Family Reference Manual, Rev. 3, September
238
I/O Retention
239
Memory Map and Register Descriptions
239
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
240
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
241
Regulator Status and Control Register (PMC_REGSC)
242
Chapter 15 Low-Leakage Wakeup Unit (LLWU)
245
Introduction
245
Features
245
Modes of Operation
246
Block Diagram
247
LLWU Signal Descriptions
248
Memory Map/Register Definition
248
LLWU Pin Enable 1 Register (LLWU_PE1)
249
LLWU Pin Enable 2 Register (LLWU_PE2)
250
LLWU Pin Enable 3 Register (LLWU_PE3)
251
LLWU Pin Enable 4 Register (LLWU_PE4)
252
LLWU Module Enable Register (LLWU_ME)
253
LLWU Flag 1 Register (LLWU_F1)
255
LLWU Flag 2 Register (LLWU_F2)
257
LLWU Flag 3 Register (LLWU_F3)
258
LLWU Pin Filter 1 Register (LLWU_FILT1)
260
LLWU Pin Filter 2 Register (LLWU_FILT2)
261
Functional Description
262
LLS Mode
263
VLLS Modes
263
Initialization
263
KL25 Sub-Family Reference Manual, Rev. 3, September
264
Chapter 16 Reset Control Module (RCM)
265
Introduction
265
Reset Memory Map and Register Descriptions
265
System Reset Status Register 0 (RCM_SRS0)
265
System Reset Status Register 1 (RCM_SRS1)
267
Reset Pin Filter Control Register (RCM_RPFC)
268
Reset Pin Filter Width Register (RCM_RPFW)
269
Chapter 17 Bit Manipulation Engine (BME)
271
Introduction
271
Overview
272
Features
272
Modes of Operation
273
External Signal Description
273
Memory Map and Register Definition
274
Functional Description
274
BME Decorated Stores
274
BME Decorated Loads
280
Additional Details on Decorated Addresses and GPIO Accesses
287
Application Information
288
Chapter 18 Miscellaneous Control Module (MCM)
291
Introduction
291
Features
291
Memory Map/Register Descriptions
291
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
292
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
293
Platform Control Register (MCM_PLACR)
293
KL25 Sub-Family Reference Manual, Rev. 3, September
294
Compute Operation Control Register (MCM_CPO)
296
Chapter 19 Micro Trace Buffer (MTB)
299
Introduction
299
Overview
299
Features
302
Modes of Operation
303
External Signal Description
303
Memory Map and Register Definition
304
MTB_RAM Memory Map
304
MTB_DWT Memory Map
316
System ROM Memory Map
326
Chapter 20 Crossbar Switch Lite (AXBS-Lite)
331
Introduction
331
Features
331
Memory Map / Register Definition
331
Functional Description
332
General Operation
332
Arbitration
333
Initialization/Application Information
334
Chapter 21 Peripheral Bridge (AIPS-Lite)
335
Introduction
335
Features
335
General Operation
336
Functional Description
336
Access Support
336
Chapter 22 Direct Memory Access Multiplexer (DMAMUX)
337
Introduction
337
Overview
337
KL25 Sub-Family Reference Manual, Rev. 3, September
337
Features
338
Modes of Operation
338
External Signal Description
339
Memory Map/Register Definition
339
Channel Configuration Register (Dmamuxx_Chcfgn)
339
Functional Description
340
DMA Channels with Periodic Triggering Capability
341
Freescale Semiconductor, Inc
342
DMA Channels with no Triggering Capability
343
Always-Enabled DMA Sources
343
Initialization/Application Information
344
Reset
344
Enabling and Configuring Sources
344
Freescale Semiconductor, Inc
345
Freescale Semiconductor, Inc
346
Freescale Semiconductor, Inc
347
Freescale Semiconductor, Inc
348
Chapter 23 DMA Controller Module
349
Introduction
349
Overview
349
Features
350
DMA Transfer Overview
351
Memory Map and Registers
352
Source Address Register (Dma_Sarn)
353
Destination Address Register (Dma_Darn)
354
DMA Status Register / Byte Count Register (Dma_Dsr_Bcrn)
355
Freescale Semiconductor, Inc
356
DMA Control Register (Dma_Dcrn)
357
Freescale Semiconductor, Inc
358
Freescale Semiconductor, Inc
359
Freescale Semiconductor, Inc
360
Functional Description
361
Transfer Requests (Cycle-Steal and Continuous Modes)
361
KL25 Sub-Family Reference Manual, Rev. 3, September
362
Dual-Address Data Transfer Mode
363
Advanced Data Transfer Controls: Auto-Alignment
364
Termination
365
Freescale Semiconductor, Inc
366
Introduction
367
Freescale Semiconductor, Inc
368
Freescale Semiconductor, Inc
369
Freescale Semiconductor, Inc
370
Modes of Operation
371
Chapter 24
372
MCG Control 1 Register (MCG_C1)
372
MCG Control 2 Register (MCG_C2)
373
MCG Control 3 Register (MCG_C3)
374
Freescale Semiconductor, Inc
375
MCG Control 5 Register (MCG_C5)
376
MCG Control 6 Register (MCG_C6)
377
MCG Status Register (MCG_S)
378
Freescale Semiconductor, Inc
379
MCG Status and Control Register (MCG_SC)
380
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
381
MCG Control 7 Register (MCG_C7)
382
MCG Control 9 Register (MCG_C9)
383
Functional Description
384
Freescale Semiconductor, Inc
385
Freescale Semiconductor, Inc
386
Freescale Semiconductor, Inc
387
MCG Internal Reference Clocks
388
Low Power Bit Usage
388
External Reference Clock
389
MCG Fixed Frequency Clock
389
KL25 Sub-Family Reference Manual, Rev. 3, September
389
MCG PLL Clock
390
MCG Auto TRIM (ATM)
390
Initialization / Application Information
391
MCG Module Initialization Sequence
391
Freescale Semiconductor, Inc
392
Using a 32.768 Khz Reference
393
Freescale Semiconductor, Inc
393
MCG Mode Switching
394
Freescale Semiconductor, Inc
395
Freescale Semiconductor, Inc
396
Freescale Semiconductor, Inc
397
Freescale Semiconductor, Inc
398
Freescale Semiconductor, Inc
399
Freescale Semiconductor, Inc
400
Freescale Semiconductor, Inc
401
Freescale Semiconductor, Inc
402
Freescale Semiconductor, Inc
403
Freescale Semiconductor, Inc
404
Chapter 25 Oscillator (OSC)
405
Introduction
405
Features and Modes
405
Block Diagram
406
OSC Signal Descriptions
406
External Crystal / Resonator Connections
407
External Clock Connections
408
Memory Map/Register Definitions
409
OSC Memory Map/Register Definition
409
Functional Description
410
OSC Module States
410
Freescale Semiconductor, Inc
411
OSC Module Modes
412
Counter
413
Reference Clock Pin Requirements
413
Reset
414
Low Power Modes Operation
414
Interrupts
414
KL25 Sub-Family Reference Manual, Rev. 3, September
415
Modes of Operation
416
Freescale Semiconductor, Inc
417
Freescale Semiconductor, Inc
418
Introduction
419
Chapter 42
420
Features
420
Chapter 26 Glossary
421
External Signal Description
422
Flash Configuration Field Description
423
Register Descriptions
424
Freescale Semiconductor, Inc
425
Freescale Semiconductor, Inc
426
Freescale Semiconductor, Inc
427
Freescale Semiconductor, Inc
428
Freescale Semiconductor, Inc
429
Freescale Semiconductor, Inc
430
Freescale Semiconductor, Inc
431
Functional Description
432
Flash Protection
433
Flash Operation in Low-Power Modes
434
Flash Reads and Ignored Writes
435
KL25 Sub-Family Reference Manual, Rev. 3, September
436
Freescale Semiconductor, Inc
437
Freescale Semiconductor, Inc
438
Freescale Semiconductor, Inc
439
Margin Read Commands
440
Flash Command Description
441
Freescale Semiconductor, Inc
442
Freescale Semiconductor, Inc
443
Freescale Semiconductor, Inc
444
Freescale Semiconductor, Inc
445
Freescale Semiconductor, Inc
446
Freescale Semiconductor, Inc
447
Freescale Semiconductor, Inc
448
Freescale Semiconductor, Inc
449
Freescale Semiconductor, Inc
450
Freescale Semiconductor, Inc
451
Freescale Semiconductor, Inc
452
Freescale Semiconductor, Inc
453
Security
454
Freescale Semiconductor, Inc
455
Reset Sequence
456
Introduction
457
Block Diagram
458
Chapter 28 ADC Signal Descriptions
459
Voltage Reference Select
460
Analog Channel Inputs (Adx)
461
ADC Status and Control Registers 1 (Adcx_Sc1N)
462
Freescale Semiconductor, Inc
463
Freescale Semiconductor, Inc
464
ADC Configuration Register 1 (Adcx_Cfg1)
465
Freescale Semiconductor, Inc
466
ADC Configuration Register 2 (Adcx_Cfg2)
467
ADC Data Result Register (Adcx_Rn)
468
Compare Value Registers (Adcx_Cvn)
469
Status and Control Register 2 (Adcx_Sc2)
470
Freescale Semiconductor, Inc
471
Status and Control Register 3 (Adcx_Sc3)
472
Freescale Semiconductor, Inc
473
ADC Offset Correction Register (Adcx_Ofs)
474
ADC Minus-Side Gain Register (Adcx_Mg)
475
ADC Plus-Side General Calibration Value Register (Adcx_Clps)
476
KL25 Sub-Family Reference Manual, Rev. 3, September
477
ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
478
ADC Minus-Side General Calibration Value Register (Adcx_Clmd)
479
ADC Minus-Side General Calibration Value Register (Adcx_Clm4)
480
ADC Minus-Side General Calibration Value Register (Adcx_Clm2)
481
ADC Minus-Side General Calibration Value Register (Adcx_Clm0)
482
Clock Select and Divide Control
483
Voltage Reference Selection
484
Conversion Control
485
Freescale Semiconductor, Inc
486
Freescale Semiconductor, Inc
487
Freescale Semiconductor, Inc
488
Freescale Semiconductor, Inc
489
Freescale Semiconductor, Inc
490
Freescale Semiconductor, Inc
491
Freescale Semiconductor, Inc
492
Automatic Compare Function
493
Calibration Function
494
Freescale Semiconductor, Inc
495
User-Defined Offset Function
496
Temperature Sensor
497
MCU Normal Stop Mode Operation
498
MCU Low-Power Stop Mode Operation
499
KL25 Sub-Family Reference Manual, Rev. 3, September
500
Application Information
501
Freescale Semiconductor, Inc
502
Sources of Error
503
Freescale Semiconductor, Inc
504
Freescale Semiconductor, Inc
505
Freescale Semiconductor, Inc
506
Freescale Semiconductor, Inc
507
Freescale Semiconductor, Inc
508
Introduction
509
Chapter 29
510
Bit DAC Key Features
510
ANMUX Key Features
511
CMP Block Diagram
512
Freescale Semiconductor, Inc
513
Memory Map/Register Definitions
514
CMP Control Register 1 (Cmpx_Cr1)
515
Freescale Semiconductor, Inc
516
CMP Filter Period Register (Cmpx_Fpr)
517
DAC Control Register (Cmpx_Daccr)
518
MUX Control Register (Cmpx_Muxcr)
519
Functional Description
520
Freescale Semiconductor, Inc
521
Freescale Semiconductor, Inc
522
Freescale Semiconductor, Inc
523
Freescale Semiconductor, Inc
524
Freescale Semiconductor, Inc
525
Freescale Semiconductor, Inc
526
Freescale Semiconductor, Inc
527
Freescale Semiconductor, Inc
528
Power Modes
529
Startup and Operation
530
Low-Pass Filter
531
Freescale Semiconductor, Inc
532
CMP Interrupts
533
CMP Asyncrhonous DMA Support
534
KL25 Sub-Family Reference Manual, Rev. 3, September
535
DAC Interrupts
536
Introduction
537
Freescale Semiconductor, Inc
538
Memory Map/Register Definition
539
Chapter 30
540
DAC Data High Register (Dacx_Datnh)
540
DAC Control Register (Dacx_C0)
541
DAC Control Register 1 (Dacx_C1)
542
Functional Description
543
DMA Operation
544
Freescale Semiconductor, Inc
545
Freescale Semiconductor, Inc
546
Introduction
547
Modes of Operation
548
KL25 Sub-Family Reference Manual, Rev. 3, September
549
TPM_EXTCLK — TPM External Clock
550
Freescale Semiconductor, Inc
551
Status and Control (Tpmx_Sc)
552
Counter (Tpmx_Cnt)
553
Modulo (Tpmx_Mod)
554
Channel (N) Status and Control (Tpmx_Cnsc)
555
Freescale Semiconductor, Inc
556
Channel (N) Value (Tpmx_Cnv)
557
Freescale Semiconductor, Inc
558
Configuration (Tpmx_Conf)
559
Freescale Semiconductor, Inc
560
Functional Description
561
Prescaler
562
Freescale Semiconductor, Inc
563
Input Capture Mode
564
Output Compare Mode
565
Freescale Semiconductor, Inc
566
Edge-Aligned PWM (EPWM) Mode
567
Center-Aligned PWM (CPWM) Mode
568
Freescale Semiconductor, Inc
569
Registers Updated from Write Buffers
570
Reset Overview
571
Freescale Semiconductor, Inc
572
Introduction
573
Features
574
KL25 Sub-Family Reference Manual, Rev. 3, September
575
Freescale Semiconductor, Inc
576
PIT Upper Lifetime Timer Register (PIT_LTMR64H)
577
Timer Load Value Register (Pit_Ldvaln)
578
Timer Control Register (Pit_Tctrln)
579
Timer Flag Register (Pit_Tflgn)
580
Freescale Semiconductor, Inc
581
Interrupts
582
Example Configuration for Chained Timers
583
Example Configuration for the Lifetime Timer
584
Freescale Semiconductor, Inc
585
Freescale Semiconductor, Inc
586
Chapter 41 Introduction
587
Chapter 33 LPTMR Signal Descriptions
588
Low Power Timer Control Status Register (Lptmrx_Csr)
589
Low Power Timer Prescale Register (Lptmrx_Psr)
590
Freescale Semiconductor, Inc
591
Low Power Timer Compare Register (Lptmrx_Cmr)
592
KL25 Sub-Family Reference Manual, Rev. 3, September
593
Freescale Semiconductor, Inc
594
LPTMR Compare
595
LPTMR Hardware Trigger
596
Introduction
597
Chapter 34
598
RTC Signal Descriptions
598
RTC Time Seconds Register (RTC_TSR)
599
RTC Time Alarm Register (RTC_TAR)
600
RTC Control Register (RTC_CR)
601
Freescale Semiconductor, Inc
602
RTC Status Register (RTC_SR)
603
RTC Lock Register (RTC_LR)
604
RTC Interrupt Enable Register (RTC_IER)
605
Functional Description
606
Time Counter
607
Time Alarm
608
Update Mode
609
KL25 Sub-Family Reference Manual, Rev. 3, September
610
Introduction
611
Chapter 35
612
USB On-The-Go
612
USB-FS Features
613
Programmers Interface
614
RX Vs. TX as a USB Target Device or USB Host
615
Addressing BDT Entries
616
Freescale Semiconductor, Inc
617
Freescale Semiconductor, Inc
618
USB Transaction
619
Freescale Semiconductor, Inc
620
Memory Map/Register Definitions
621
Freescale Semiconductor, Inc
622
Peripheral ID Register (Usbx_Perid)
623
Peripheral ID Complement Register (Usbx_Idcomp)
624
Peripheral Additional Info Register (Usbx_Addinfo)
625
OTG Interrupt Control Register (Usbx_Otgicr)
626
OTG Status Register (Usbx_Otgstat)
627
OTG Control Register (Usbx_Otgctl)
628
Interrupt Status Register (Usbx_Istat)
629
Interrupt Enable Register (Usbx_Inten)
630
Error Interrupt Status Register (Usbx_Errstat)
631
Error Interrupt Enable Register (Usbx_Erren)
632
KL25 Sub-Family Reference Manual, Rev. 3, September
633
Control Register (Usbx_Ctl)
634
Address Register (Usbx_Addr)
635
BDT Page Register 1 (Usbx_Bdtpage1)
636
Frame Number Register High (Usbx_Frmnumh)
637
SOF Threshold Register (Usbx_Softhld)
638
BDT Page Register 2 (Usbx_Bdtpage2)
639
USB Control Register (Usbx_Usbctrl)
640
USB OTG Observe Register (Usbx_Observe)
641
USB OTG Control Register (Usbx_Control)
642
Frame Adjust Register (Usbx_Usbfrmadjust)
643
OTG and Host Mode Operation
644
Freescale Semiconductor, Inc
645
Freescale Semiconductor, Inc
646
On-The-Go Operation
647
OTG Dual Role a Device Operation
648
OTG Dual Role B Device Operation
649
Freescale Semiconductor, Inc
650
Introduction
651
Overview
652
Modes of Operation
653
KL25 Sub-Family Reference Manual, Rev. 3, September
654
Introduction
655
Modes of Operation
656
Chapter 37
657
Block Diagrams
657
Freescale Semiconductor, Inc
658
External Signal Description
659
SPSCK — SPI Serial Clock
660
Memory Map and Register Descriptions
661
Freescale Semiconductor, Inc
662
SPI Control Register 2 (Spix_C2)
663
SPI Baud Rate Register (Spix_Br)
664
SPI Status Register (Spix_S)
665
Freescale Semiconductor, Inc
666
SPI Data Register (Spix_D)
667
SPI Match Register (Spix_M)
668
Master Mode
669
Slave Mode
670
SPI Transmission by DMA
671
Freescale Semiconductor, Inc
672
SPI Clock Formats
673
Freescale Semiconductor, Inc
674
Freescale Semiconductor, Inc
675
SPI Baud Rate Generation
676
Special Features
677
Freescale Semiconductor, Inc
678
Error Conditions
679
Freescale Semiconductor, Inc
680
Reset
681
KL25 Sub-Family Reference Manual, Rev. 3, September
682
Initialization/Application Information
683
Pseudo-Code Example
684
Freescale Semiconductor, Inc
685
Freescale Semiconductor, Inc
686
Introduction
687
Modes of Operation
688
Memory Map and Register Descriptions
689
Chapter 38
690
I2C Address Register 1 (I2Cx_A1)
690
I2C Frequency Divider Register (I2Cx_F)
691
I2C Control Register 1 (I2Cx_C1)
692
Freescale Semiconductor, Inc
693
I2C Status Register (I2Cx_S)
694
I2C Data I/O Register (I2Cx_D)
695
I2C Control Register 2 (I2Cx_C2)
696
I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
697
I2C Range Address Register (I2Cx_Ra)
698
I2C Smbus Control and Status Register (I2Cx_Smb)
699
Freescale Semiconductor, Inc
700
I2C Address Register 2 (I2Cx_A2)
701
Functional Description
702
Freescale Semiconductor, Inc
703
Freescale Semiconductor, Inc
704
Freescale Semiconductor, Inc
705
Freescale Semiconductor, Inc
706
Bit Address
707
Freescale Semiconductor, Inc
708
Address Matching
709
KL25 Sub-Family Reference Manual, Rev. 3, September
710
Freescale Semiconductor, Inc
711
Resets
712
Freescale Semiconductor, Inc
713
Programmable Input Glitch Filter
714
Address Matching Wakeup
715
DMA Support
716
Freescale Semiconductor, Inc
717
Freescale Semiconductor, Inc
718
Freescale Semiconductor, Inc
719
Freescale Semiconductor, Inc
720
Introduction
721
Modes of Operation
722
Freescale Semiconductor, Inc
723
Register Definition
724
Chapter 39
725
UART Baud Rate Register High (Uartx_Bdh)
725
UART Baud Rate Register Low (Uartx_Bdl)
726
Freescale Semiconductor, Inc
727
UART Control Register 2 (Uartx_C2)
728
UART Status Register 1 (Uartx_S1)
729
Freescale Semiconductor, Inc
730
UART Status Register 2 (Uartx_S2)
731
Freescale Semiconductor, Inc
732
UART Control Register 3 (Uartx_C3)
733
UART Data Register (Uartx_D)
734
UART Match Address Registers 1 (Uartx_Ma1)
735
UART Match Address Registers 2 (Uartx_Ma2)
736
UART Control Register 5 (Uartx_C5)
737
Functional Description
738
KL25 Sub-Family Reference Manual, Rev. 3, September
739
Receiver Functional Description
740
Freescale Semiconductor, Inc
741
Freescale Semiconductor, Inc
742
Additional UART Functions
743
Freescale Semiconductor, Inc
744
Interrupts and Status Flags
745
Freescale Semiconductor, Inc
746
Introduction
747
Modes of Operation
748
Freescale Semiconductor, Inc
749
Register Definition
750
Chapter 40
751
UART Baud Rate Register: High (Uartx_Bdh)
751
UART Control Register 1 (Uartx_C1)
752
UART Control Register 2 (Uartx_C2)
753
Freescale Semiconductor, Inc
754
UART Status Register 1 (Uartx_S1)
755
UART Status Register 2 (Uartx_S2)
756
Freescale Semiconductor, Inc
757
UART Control Register 3 (Uartx_C3)
758
Freescale Semiconductor, Inc
759
UART Data Register (Uartx_D)
760
Functional Description
761
Baud Rate Generation
762
Freescale Semiconductor, Inc
763
Receiver Functional Description
764
Freescale Semiconductor, Inc
765
Freescale Semiconductor, Inc
766
Interrupts and Status Flags
767
DMA Operation
768
KL25 Sub-Family Reference Manual, Rev. 3, September
769
Freescale Semiconductor, Inc
770
Introduction
771
Modes of Operation
772
Memory Map and Register Definition
773
Freescale Semiconductor, Inc
774
Port Data Output Register (Gpiox_Pdor)
775
Port Set Output Register (Gpiox_Psor)
776
Port Toggle Output Register (Gpiox_Ptor)
777
Port Data Direction Register (Gpiox_Pddr)
778
Freescale Semiconductor, Inc
779
Port Data Output Register (Fgpiox_Pdor)
780
Port Set Output Register (Fgpiox_Psor)
781
Port Toggle Output Register (Fgpiox_Ptor)
782
Port Data Direction Register (Fgpiox_Pddr)
783
Ioport
784
Introduction
785
KL25 Sub-Family Reference Manual, Rev. 3, September
786
External Signal Description
787
Freescale Semiconductor, Inc
788
Freescale Semiconductor, Inc
789
Freescale Semiconductor, Inc
790
Freescale Semiconductor, Inc
791
TSI DATA Register (Tsix_Data)
792
TSI Threshold Register (Tsix_Tshd)
793
Capacitance Measurement
794
Freescale Semiconductor, Inc
795
Freescale Semiconductor, Inc
796
TSI Measurement Result
797
Scan Times
798
Current Source
799
Wake up MCU from Low Power Modes
800
KL25 Sub-Family Reference Manual, Rev. 3, September
801
Freescale Semiconductor, Inc
802
Freescale Semiconductor, Inc
803
Freescale Semiconductor, Inc
804
Freescale Semiconductor, Inc
805
Freescale Semiconductor, Inc
807
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