Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration information.
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space.
(Not all peripheral slots might be used. See the chip configuration chapter and memory
map chapter for details on slot assignment.) The bridge includes separate clock enable
inputs for each of the slots to accommodate slower peripherals.
21.1.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Dedicated clock enables for independently configurable peripherals allow each on- or
off-platform peripheral to operate at any integer-divisible speed less than or equal to
the system clock frequency.
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 335
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