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NXP Semiconductors MKL25Z128VLK4 - Error Interrupt Enable Register (Usbx_Erren)

NXP Semiconductors MKL25Z128VLK4
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USBx_ERRSTAT field descriptions (continued)
Field Description
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted
from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
3
DFN8
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
2
CRC16
This bit is set when a data packet is rejected due to a CRC16 error.
1
CRC5EOF
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set
the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOSTMODEEN=1), this interrupt detects End Of Frame
(EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the SOF
counter reaches zero. This interrupt is useful when developing USB packet scheduling software to ensure
that no USB transactions cross the start of the next frame.
0
PIDERR
This bit is set when the PID check field fails.
35.4.12 Error Interrupt Enable register (USBx_ERREN)
Contains enable bits for each of the error interrupt sources within the USB module.
Setting any of these bits enables the respective interrupt source in ERRSTAT. Each bit is
set as soon as the error conditions is detected. Therefore, the interrupt does not typically
correspond with the end of a token being processed. This register contains the value of
0x00 after a reset.
Address: 4007_2000h base + 8Ch offset = 4007_208Ch
Bit 7 6 5 4 3 2 1 0
Read
BTSERREN
0
DMAERREN BTOERREN DFN8EN CRC16EN
CRC5EOFE
N
PIDERREN
Write
Reset
0 0 0 0 0 0 0 0
USBx_ERREN field descriptions
Field Description
7
BTSERREN
BTSERR Interrupt Enable
0 Disables the BTSERR interrupt.
1 Enables the BTSERR interrupt.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
DMAERREN
DMAERR Interrupt Enable
0 Disables the DMAERR interrupt.
1 Enables the DMAERR interrupt.
Table continues on the next page...
Memory map/Register definitions
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
632 Freescale Semiconductor, Inc.

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