3.8.1.4 Global Timebase
Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit.
TPM1 is configured as the global time when this option is enabled.
3.8.1.5 TPM Interrupts
The TPM has multiple sources of interrupt. However, these sources are OR'd together to
generate a single interrupt request to the interrupt controller. When an TPM interrupt
occurs, read the TPM status registers to determine the exact interrupt source.
3.8.2 PIT Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Peripheral
bridge
Periodic interrupt
timer
Figure 3-25. PIT configuration
Table 3-39. Reference links to related information
Topic Related module Reference
Full description PIT PIT
System memory map System memory map
Clocking Clock Distribution
Power management Power management
3.8.2.1 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA channel mux as shown in the table
below.
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 87
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