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NXP Semiconductors MKL25Z128VLK4 - Functional Description; Pin Control

NXP Semiconductors MKL25Z128VLK4
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PORTx_ISFR field descriptions
Field Description
31–0
ISF
Interrupt Status Flag
Each bit in the field indicates the detection of the configured interrupt of the same number as the field.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
11.6 Functional description
11.6.1 Pin control
Each port pin has a corresponding pin control register, PORT_PCRn, associated with it.
The upper half of the pin control register configures the pin's capability to either interrupt
the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a
logic level occurring on the port pin. It also includes a flag to indicate that an interrupt
has occurred.
The lower half of the pin control register configures the following functions for each pin
within the 32-bit port.
Pullup or pulldown enable on selected pins
Drive strength and slew rate configuration on selected pins
Passive input filter enable on selected pins
Pin Muxing mode
The functions apply across all digital Pin Muxing modes and individual peripherals do
not override the configuration in the pin control register. For example, if an I
2
C function
is enabled on a pin, that does not override the pullup configuration for that pin.
When the Pin Muxing mode is configured for analog or is disabled, all the digital
functions on that pin are disabled. This includes the pullup and pulldown enables, and
passive filter enable.
The configuration of each pin control register is retained when the PORT module is
disabled.
Chapter 11 Port control and interrupts (PORT)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 187

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