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NXP Semiconductors MKL25Z128VLK4 - DMA Operation

NXP Semiconductors MKL25Z128VLK4
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30.5.1.2 Modes of DAC data buffer operation
The following table describes the different modes of data buffer operation for the DAC
module.
Table 30-23. Modes of DAC data buffer operation
Modes Description
Buffer Normal mode
This is the default mode. The buffer works as a circular buffer.
The read pointer increases by one, every time the trigger
occurs. When the read pointer reaches the upper limit, it goes
to 0 directly in the next trigger event.
Buffer One-time Scan mode
The read pointer increases by 1 every time the trigger occurs.
When it reaches the upper limit, it stops there. If read pointer
is reset to the address other than the upper limit, it will
increase to the upper address and stop there again.
NOTE: If the software set the read pointer to the upper limit,
the read pointer will not advance in this mode.
30.5.2 DMA operation
When DMA is enabled, DMA requests are generated instead of interrupt requests. The
DMA Done signal clears the DMA request.
The status register flags are still set and are cleared automatically when the DMA
completes.
30.5.3 Resets
During reset, the DAC is configured in the default mode and is disabled.
30.5.4 Low-Power mode operation
The following table shows the wait mode and the stop mode operation of the DAC
module.
Table 30-24. Modes of operation
Modes of operation Description
Wait mode The DAC will operate normally, if enabled.
Table continues on the next page...
Functional description
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
544 Freescale Semiconductor, Inc.

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