NXP Semiconductors MKL25Z128VLK4 - UART Control Register 2 (Uartx_C2)

UARTx_C1 field descriptions (continued)
Field Description
This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set, the receiver input
is internally connected to the TxD pin and RSRC determines whether this connection is also connected to
the transmitter output.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not
use the RxD pins.
1 Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
4
M
9-Bit or 8-Bit Mode Select
0 Normal - start + 8 data bits (lsb first) + stop.
1 Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
3
WAKE
Receiver Wakeup Method Select
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select
Setting this bit to 1 ensures that the stop bits and logic 1 bits at the end of a character do not count toward
the 10 or 11 bit times of logic high level needed by the idle line detection logic.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of
the data character, eighth or ninth data bit, is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number
of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the
data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
40.2.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base address + h offset
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
Chapter 40 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 753