NXP Semiconductors MKL25Z128VLK4 - Modes of Operation

40.1.2 Modes of operation
See Section Functional description for details concerning UART operation in these
modes:
• 8- and 9-bit data modes
• Stop mode operation
• Loop mode
• Single-wire mode
40.1.3 Block diagram
The following figure shows the transmitter portion of the UART.
PE
PT
H 8 7 6 5 4 3 2 1 0 L
11-BIT TRANSMIT SHIFT REGISTER
STOP
START
T8
TDRE
TIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
UART DATA REGISTER (UART_D)
LOAD FROM UART_D
SHIFT ENABLE
PREAMBLE (ALL 1s)
BREAK (ALL 0s)
TRANSMITTER CONTROL
M
INTERNAL BUS
SBR12–SBR0
BAUD DIVIDER
÷
16
TDRE INTERRUPT/DMA
TC INTERRUPT/DMA
MODULE
LOOP
RSRC
CLOCK
TE
TO
CONTROL
RECEIVER
LOOPS
TXINV
TxD Pin Control
TXDIR
TxD
SHIFT DIRECTION
TXINV
DMA done
REQUEST
Tx Pin Logic
REQUEST
Figure 40-1. UART transmitter block diagram
The following figure shows the receiver portion of the UART.
Introduction
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
748 Freescale Semiconductor, Inc.